verilog小白，故常常有各種ERROR和WARNING。記錄一下平時自己遇到的問題，希望有用。。。
REEOR1：
Unexpected EOF.
翻譯：意外的文件結束。
原因：module和endmodule沒有匹配。（有時候網上複製下來的代碼常常會出現這樣的問題）
REEOR2：
Port connections cannot be mixed ordered and named
翻譯：端口連接不能混合命令和命名
example ：
Myclock1 c2(
.clk(clk),
.clk1(clk2),
);
原因：調用module的時候最後一個端口後面多了一個逗號。。。好吧，是一個很傻的錯誤。再次證明了我是初學者。。。
ERROR3:
A clock IOB / BUFGMUX clock component pair have been found
that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
IOB component <OE> is placed at site <PAD164>. The corresponding BUFG
component <OE_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y10>. There is only a
select set of IOBs that can use the fast path to the Clocker buffer, and they
are not being used. You may want to analyze why this problem exists and
correct it. If this sub optimal condition is acceptable for this design, you
may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this
message to a WARNING and allow your design to continue. However, the use of
this override is highly discouraged as it may lead to very poor timing
results. It is recommended that this error condition be corrected in the
design. A list of all the COMP.PINs used in this clock placement rule is
listed below. These examples can be used directly in the .ucf file to
ide this clock rule.
< NET "OE" CLOCK_DEDICATED_ROUTE = FALSE; >
原因：將組合邏輯電路的值作爲了時鐘信號（比如always的敏感變量是組合邏輯電路的值），一般是加入.ucf文件之後出現的問題，解決方法是將NET "OE" CLOCK_DEDICATED_ROUTE = FALSE;這一段語句加入.ucf文件中去。但是即使這樣做，還是會有一個warning，因爲組合邏輯電路信號會因爲開關抖動之類的原因產生毛刺，造成always的錯誤判斷。verilog 不建議這種寫法，可以考慮將敏感變量設爲自帶的時鐘信號，在always塊內部使用組合邏輯電路的值