首次修改成功uboot-2010.06。
。
2，這部分大致說明需要修改的文件及所在位置，至於爲什麼這樣修改，以及需要查看的相關手冊，不在敘述。
- 修改SDRAM的配置
# vi board/samsung/Nissa2440/lowlevel_init.S54 #define B1_BWSCON (DW16) 55 #define B2_BWSCON (DW16) 56 #define B3_BWSCON (DW16 + WAIT + UBLB) 57 #define B4_BWSCON (DW16) 58 #define B5_BWSCON (DW8) 59 #define B6_BWSCON (DW32) 60 #define B7_BWSCON (DW32)126 #define REFCNT 0x4f4 - 時鐘設置
# vi arch/arm/cpu/arm920t/start.S108 start_code: 109 /* 110 * set the cpu to SVC32 mode 111 */ 112 mrs r0, cpsr 113 bic r0, r0, #0x1f 114 orr r0, r0, #0xd3 115 msr cpsr, r0 116 117 #define pWTCON 0x53000000 118 #define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ 119 #define INTSUBMSK 0x4A00001C 120 #define CLKDIVN 0x4C000014 /* clock divisor register */ 121 #define MPLLCON 0x4c000004 122 #define UPLLCON 0x4c000008 123 124 125 ldr r0, =pWTCON 126 mov r1, #0x0 127 str r1, [r0]128 129 /* 130 * mask all IRQs by setting all bits in the INTMR - default 131 */ 132 mov r1, #0xffffffff 133 ldr r0, =INTMSK 134 str r1, [r0] 135 136 #if defined(CONFIG_S3C2440) /*在include/configs/Nissa2440.h中定義：#define CONFIG_S3C2440 1 137 ldr r1, =0x7ff 138 ldr r0, =INTSUBMSK 139 str r1, [r0] 140 #endif 141 /* 142 * we do sys-critical inits only at reboot, 143 * not when booting from ram! 144 */ 145 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 146 /* bl cpu_init_crit */ 147 #endif - 重新配置時鐘
# vi board/samsung/Nissa2440/Nissa2440.c58 /* S3C2440: Mpll = (2*m * Fin) / (p * 2^s), UPLL = (m * Fin) / (p * 2^s) 59 * m = M (the value for divider M)+ 8, p = P (the value for divider P) + 2 60 */ 61 /* Fin = 12.0000MHz */ 62 #define S3C2440_MPLL_400MHZ ((0x5c<<12)|(0x01<<4)|(0x01)) //HJ 400MHz 63 #define S3C2440_MPLL_405MHZ ((0x7f<<12)|(0x02<<4)|(0x01)) //HJ 405MHz 64 #define S3C2440_MPLL_440MHZ ((0x66<<12)|(0x01<<4)|(0x01)) //HJ 440MHz 65 #define S3C2440_MPLL_480MHZ ((0x98<<12)|(0x02<<4)|(0x01)) //HJ 480MHz 66 #define S3C2440_MPLL_200MHZ ((0x5c<<12)|(0x01<<4)|(0x02)) 67 #define S3C2440_MPLL_100MHZ ((0x5c<<12)|(0x01<<4)|(0x03)) 68 69 #define S3C2440_UPLL_48MHZ ((0x38<<12)|(0x02<<4)|(0x02)) //HJ 100MHz 70 71 #define S3C2440_CLKDIV 0x05 /* FCLK:HCLK:PCLK = 1:4:8, UCLK = UPLL * / //HJ 100MHz 72 #define S3C2440_CLKDIV136 0x07 /* FCLK:HCLK:PCLK = 1:3:6, UCLK = UPLL * / //HJ 133MHz 73 #define S3C2440_CLKDIV188 0x04 /* FCLK:HCLK:PCLK = 1:8:8 */ 74 #define S3C2440_CAMDIVN188 ((0<<8)|(1<<9)) /* FCLK:HCLK:PCLK = 1:8:8 */ 75 /* Fin = 16.9344MHz */ 76 #define S3C2440_MPLL_399MHz ((0x6e<<12)|(0x03<<4)|(0x01)) 77 #define S3C2440_UPLL_48MHZ_Fin16MHz ((60<<12)|(4<<4)|(2)) 78 79 /* S3C2410: Mpll,Upll = (m * Fin) / (p * 2^s) 80 * m = M (the value for divider M)+ 8, p = P (the value for divider P) + 2 81 */ 82 #define S3C2410_MPLL_200MHZ ((0x5c<<12)|(0x04<<4)|(0x00)) 83 #define S3C2410_UPLL_48MHZ ((0x28<<12)|(0x01<<4)|(0x02)) 84 #define S3C2410_CLKDIV 0x03 /* FCLK:HCLK:PCLK = 1:2:4 */ 85 86 static inline void delay (unsigned long loops) //到這行爲止
133 gpio->GPHUP = 0x000007FF; 134 135 /* arch number of SMDK2410-Board */ 136 /* support both of S3C2410 and S3C2440 */ 137 if ((gpio->GSTATUS1 == 0x32410000) || (gpio->GSTATUS1 == 0x32410002)) 138 { 139 /* arch number of SMDK2410-Board */ 140 gd->bd->bi_arch_number = MACH_TYPE_SMDK2410; 141 } 142 else 143 { 144 /* arch number of SMDK2440-Board */ 145 gd->bd->bi_arch_number = MACH_TYPE_S3C2440; 146 } 147 148 /* adress of boot parameters */ 149 gd->bd->bi_boot_params = 0x30000100; 150
- 修改speed.c
# vi arch/arm/cpu/arm920t/s3c24x0/speed.c32 #include <common.h> 33 DECLARE_GLOBAL_DATA_PTR; 34 35 #ifdef CONFIG_S3C24X065 m = ((r & 0xFF000) >> 12) + 8; 66 p = ((r & 0x003F0) >> 4) + 2; 67 s = r & 0x3; 68 69 /* support both of S3C2410 and S3C2440*/ 70 if (gd->bd->bi_arch_number == MACH_TYPE_SMDK2410) 71 return((CONFIG_SYS_CLK_FREQ * m) / (p << s)); 72 else 73 return((CONFIG_SYS_CLK_FREQ * m * 2) / (p << s)); /* S3C2440 */ 74 }76 /* return FCLK frequency */ 77 ulong get_FCLK(void) 78 { 79 return get_PLLCLK(MPLL); 80 } 81 82 83 /* for s3c2440 */ 84 #define S3C2440_CLKDIVN_PDIVN (1<<0) 85 #define S3C2440_CLKDIVN_HDIVN_MASK (3<<1) 86 #define S3C2440_CLKDIVN_HDIVN_1 (0<<1) 87 #define S3C2440_CLKDIVN_HDIVN_2 (1<<1) 88 #define S3C2440_CLKDIVN_HDIVN_4_8 (2<<1) 89 #define S3C2440_CLKDIVN_HDIVN_3_6 (3<<1) 90 #define S3C2440_CLKDIVN_UCLK (1<<3) 91 92 #define S3C2440_CAMDIVN_CAMCLK_MASK (0xf<<0) 93 #define S3C2440_CAMDIVN_CAMCLK_SEL (1<<4) 94 #define S3C2440_CAMDIVN_HCLK3_HALF (1<<8) 95 #define S3C2440_CAMDIVN_HCLK4_HALF (1<<9) 96 #define S3C2440_CAMDIVN_DVSEN (1<<12) 97 98 /* return HCLK frequency */99 ulong get_HCLK(void) 100 { 101 struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); 102 unsigned long clkdiv; 103 unsigned long camdiv; 104 int hdiv = 1; 105 /* support both of S3C2410 and S3C2440 */ 106 if (gd->bd->bi_arch_number == MACH_TYPE_SMDK2410) 107 return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK()); 108 else 109 { 110 clkdiv = clk_power->CLKDIVN; 111 camdiv = clk_power->CAMDIVN; 112 /* work out clock scalings */ 113 switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) { 114 case S3C2440_CLKDIVN_HDIVN_1: 115 hdiv = 1; 116 break; 117 case S3C2440_CLKDIVN_HDIVN_2: 118 hdiv = 2; 119 break; 120 case S3C2440_CLKDIVN_HDIVN_4_8: 121 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4; 122 break; 123 case S3C2440_CLKDIVN_HDIVN_3_6: 124 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3; 125 break; 126 } 127 return get_FCLK() / hdiv; 128 } 129 }130 /* return PCLK frequency */ 131 ulong get_PCLK(void) 132 { 133 struct s3c24x0_clock_power * const clk_power = s3c24x0_get_base_clock_po wer(); 134 unsigned long clkdiv; 135 unsigned long camdiv; 136 int hdiv = 1; 137 /* support both of S3C2410 and S3C2440 */ 138 if (gd->bd->bi_arch_number == MACH_TYPE_SMDK2410) 139 return((clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK()); 140 else { 141 clkdiv = clk_power->CLKDIVN; 142 camdiv = clk_power->CAMDIVN; 143 /* work out clock scalings */ 144 switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) { 145 case S3C2440_CLKDIVN_HDIVN_1: 146 hdiv = 1; 147 break; 148 case S3C2440_CLKDIVN_HDIVN_2: 149 hdiv = 2; 150 break; 151 case S3C2440_CLKDIVN_HDIVN_4_8: 152 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4; 153 break; 154 case S3C2440_CLKDIVN_HDIVN_3_6: 155 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3; 156 break; 157 } 158 159 return get_FCLK() / hdiv / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1); 160 } 161 } 162 - 重新定義S3C24X0_CLOCK_POWER結構體
# vi include/asm/arch-s3c24x0/s3c24x0.h118 struct s3c24x0_clock_power { 119 u32 LOCKTIME; 120 u32 MPLLCON; 121 u32 UPLLCON; 122 u32 CLKCON; 123 u32 CLKSLOW; 124 u32 CLKDIVN; 125 u32 CAMDIVN; 126 }; - 修改程序執行地址
# vi board/samsung/Nissa2440/config.mk 23
24
25 TEXT_BASE = 0x33000000