二進制加法器的VHDL程序

在上一篇文章中我們討論了二進制加法器的原理，在此我們給出二進制加法器的VHDL描述：

library IEEE;
use IEEE.std_logic_1164.all;

package std_logic_arith is 
    type unsigned is array (natural range<>) of std_logic;
    type signed is array (natural range<>) of std_logic;
    type builtin_subprogram : string;
    
    function "+"(L: signed; R: signed) return signed;
    attribute builtin_subprogram of 
        "+"[signed, signed return signed] : function is "stdarith_plus_sss"; --不知這句
                                                                             --什麼意思
end std_logic_arith;

package body std_logic_arith is
    function plus(A,B: signed) return signed is
        variable carry : std_ulogic;
        variable BV, sum : signed(A'left downto 0);
    begin
        if (A(A'left) = 'X' or B(B'left) = 'X') then
                sum := (others => 'X');
                return (sum;
        end if;
        carry := '0';
        BV    := B;

        for i in 0 to A'left loop
            sum(i) := A(i) xor BV(i) xor carry;
            carry  := (A(i) and BV(i)) or ((A(i) or BV(i)) and carry);
        end loop;                         --for...loop語句最終實現爲具體的數字門電路結構
                                          --所以當A,B位數很大時加法器的結構也就會變得很複雜
                                          --然而，這是符合設計加法器的數字電路理論的
        return sum;
    end ;

    function "+"(L: signed; R: signed) return std_logic_vector is
        constant length : integer := max(L'length,R'length);
    begin
        return std_logic_vector(plus(conv_signed(L,length), conv_signed(R,length)));
    end;

此二進制加法器設計摘自IEEE.STD_LOGIC_ARITH數據包，在定點數，浮點數加法設計中最終都會調用此加法器作爲加法運算的核心。