fpga 流水線算法設計實例

所謂流水線設計實際上就是把規模較大、層次較多的組合邏輯電路分爲幾個級，在每一級插入寄存器組暫存中間數據。K 級的流水線就是從組合邏輯的輸入到輸出恰好有 K 個寄存器組（分爲 K 級，每一級都有一個寄存器組）上一級的輸出是下一級的輸入而又無反饋的電路。

非流水線設計：

 

流水線設計：

四級8位加法器的設計原理圖：

對應的VHDL描述：

LIBRARY ieee;
   USE ieee.std_logic_1164.all;
   USE ieee.std_logic_unsigned.all;


ENTITY adder_8bits_4steps IS
   PORT (
      cin_a    : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
      cin_b    : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
      c_in     : IN STD_LOGIC;
      clk      : IN STD_LOGIC;
      c_out    : OUT STD_LOGIC;
      sum_out  : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
   );
END adder_8bits_4steps;

ARCHITECTURE trans OF adder_8bits_4steps IS
   
   
   SIGNAL sum_out_t1 : STD_LOGIC_VECTOR(2 DOWNTO 0);
   SIGNAL sum_out_t2 : STD_LOGIC_VECTOR(4 DOWNTO 0);
   SIGNAL sum_out_t3 : STD_LOGIC_VECTOR(6 DOWNTO 0);
   signal sum_out_t4 : std_logic_vector(8 downto 0);
BEGIN
   
   PROCESS (clk)
   BEGIN
      IF (clk'EVENT AND clk = '1') THEN
         sum_out_t1 <= ('0' & cin_a(1 DOWNTO 0)) + ('0' & cin_b(1 DOWNTO 0)) + ("00" & c_in);
      END IF;
   END PROCESS;
   
   
   PROCESS (clk)
   BEGIN
      IF (clk'EVENT AND clk = '1') THEN
        sum_out_t2 <= (('0' & cin_a(3 DOWNTO 2)) + ('0' & cin_b(3 DOWNTO 2)) + ("00" & sum_out_t1));
      END IF;
   END PROCESS;
   
   
   PROCESS (clk)
   BEGIN
      IF (clk'EVENT AND clk = '1') THEN
          sum_out_t3 <= (('0' & cin_a(5 DOWNTO 4)) + ('0' & cin_b(5 DOWNTO 4)) + ("00" & sum_out_t2));
      END IF;
   END PROCESS;
   
   
   PROCESS (clk)
   BEGIN
      IF (clk'EVENT AND clk = '1') THEN
          sum_out_t4 <= (('0' & cin_a(7 DOWNTO 6)) + ('0' & cin_b(7 DOWNTO 6)) + ("00" & sum_out_t3));
      END IF;
   END PROCESS;

   c_out <= sum_out_t4(8);
   sum_out <= sum_out_t4(7 downto 0);
   
   
END trans;