PCI控制
目錄
器及橋關係解讀
1.PCI控制器解讀
選擇P1010使用的PCIE控制器驅動代碼進行解讀，該控制器爲QorIqPcie控制器，而非mpc85xx_pcie控制器，後者用於P2020。
- 驅動文件路徑
- 函數接口概要
- 初始化步驟
LOCAL struct drvBusFuncs pexFuncs =
{
pexInstInit, /* devInstanceInit */
pexInstInit2, /* devInstanceInit2 */
pexInstConnect /* devInstanceConnect */
};
- 提供的方法
主要概括爲 ： 配置空間讀寫，控制信息獲取，MSI中斷寫入，MSI中斷使能\關閉等。
LOCAL struct vxbDeviceMethod pexMethodList[] =
{
DEVMETHOD(busCtlrDevCfgRead, pexMethodDevCfgRead),
DEVMETHOD(busCtlrDevCfgWrite, pexMethodDevCfgWrite),
DEVMETHOD(busCtlrDevCtlr, pexDevControl),
DEVMETHOD(busCtlrBaseAddrCvt, pexBaseAddressConvert),
DEVMETHOD(vxbIntDynaVecProgram, pexMSIProgram),
DEVMETHOD(vxbIntDynaVecEnable, vxbPciMSIEnable),
DEVMETHOD(vxbIntDynaVecDisable, vxbPciMSIDisable),
DEVMETHOD(vxbIntDynaVecErase, vxbPciMSIErase),
DEVMETHOD(vxbIntDynaVecGet, vxbPciMSIGet),
DEVMETHOD(vxbDevIntCapabCheck, vxbPciDevIntCapabCheck),
{ PCI_CONTROLLER_METHOD_CFG_INFO, (FUNCPTR)pexConfigInfo},
{ PCI_CONTROLLER_METHOD_INTERRUPT_INFO, (FUNCPTR)pexInterruptInfo},
DEVMETHOD(vxbDrvUnlink, pexInstUnlink),
DEVMETHOD_END
};
1.1配置空間讀
LOCAL STATUS pexMethodDevCfgRead
(
VXB_DEVICE_ID pDev, /* device info */
PCI_HARDWARE * pPciDev, /* PCI device info */
UINT32 byteOffset, /* offset into cfg space */
UINT32 transactionSize, /* transaction size, in bytes */
void * pDataBuf /* buffer to read-from/write-to */
)
{
根據 pPciDev 獲取bus dev fuction
......
核心代碼爲
CSR_WRITE_4(pDev, PEX_CFG_ADDR, addr | PEX_CFGADDR_EN);
val = CSR_READ_4(pDev, PEX_CFG_DATA);
CSR_WRITE_4(pDev, PEX_CFG_ADDR, 0);
if (CSR_READ_4(pDev, PEX_ERR_DR) & PEX_ERRDR_ICCA)
{
retVal = ERROR;
CSR_WRITE_4(pDev, PEX_ERR_DR, PEX_ERRDR_ICCA);
}
操作PCIE控制器寄存器實現
其中寄存器相關定義
#define PEX_CFG_ADDR 0x000 /* PCI config address */
#define PEX_CFG_DATA 0x004 /* PCI config data */
#define PEX_OTBC_TMO 0x00C /* Outbound completion timeout */
#define PEX_CRTY_TMO 0x010 /* Configuration retry timeout */
#define PEX_CFG 0x014 /* Configuration register */
#define PEX_PMEMES_DR 0x020 /* PME & message direct */
#define PEX_PMEMES_IDR 0x024 /* Interrupt disable */
#define PEX_PMEMES_IER 0x028 /* Interrupt enable */
#define PEX_PMCR 0x02C /* Power management command */
}
1.2配置空間寫
LOCAL STATUS pexMethodDevCfgWrite
(
VXB_DEVICE_ID pDev, /* device info */
PCI_HARDWARE * pPciDev, /* PCI device info */
UINT32 byteOffset, /* offset into cfg space */
UINT32 transactionSize, /* transaction size, in bytes */
UINT32 data /* data write to the offset */
)
{
同讀，按照芯片手冊操作PCIE控制器寄存器實現
}
1.3設備控制方法
這個函數不知道什麼時候被調用，在函數實現體中加logMsg，沒看到控制檯有對應打印信息。
LOCAL STATUS pexDevControl
(
VXB_DEVICE_ID pDev,
pVXB_DEVCTL_HDR pBusDevControl
)
{
獲取父設備
獲取父設備drv_ctrl
獲取父設備中斷消息
pBusDev = vxbDevParent(pDev);
pDrvCtrl = pBusDev->pDrvCtrl;
pciIntInfo = (struct pciIntrEntry *)(pDev->pIntrInfo);
訪問類型case
switch (pBusDevControl->vxbAccessId)
{
//中斷向量獲取
Case VXB_ACCESS_INT_VEC_GET：
If(具備MSI能力)
賦值爲動態中斷
Else
普通中斷
Break;
case中斷使能:
Break;
case中斷關閉:
Break;
case中斷連接connect:
Break;
}
}
1.4寫中斷向量
#define PCI_MSI_CTL 0x02 /* Offset of MSI control register */
#define PCI_MSI_CTL_ENABLE 0x01 /* MSI enable */
#define PCI_MSI_CTL_MSG_ALLOC 0x70 /* Number of Messages allocated */
#define PCI_MSI_CTL_MSG_MAX 0x0E /* Maximum Messages Allowed */
#define PCI_MSI_CTL_64BIT 0x80 /* 64-bit addresses allowed */
#define PCI_MSI_CTL_MASK 0x100 /* Per-vector masking capable */
/* Message Address Register */
#define PCI_MSI_ADDR_LO 0x04 /* Offset of MSI Address Lower 32 bits */
/* Used for 32-bit MSI */
#define PCI_MSI_ADDR_HI 0x08 /* Offset of MSI Address Upper 32 bits */
pexMSIProgram
{
vxbPciMSIProgram （src/vxBus/vxbPci.c）
->獲取msicnt
->Vectype判斷
If(MSIX)
{
vxbPciMSIXMultiProgram
}
else
{
處理 02 04 08 寄存器
MSI 處理
vxbPciMSIMultiProgram
-> 獲取父設備pDev
- >獲取父設備能力
vxbPciConfigExtCapFind（0x5寄存器）
vxbPciBusCfgRead (pDev, (UINT32)(msiOffset + PCI_MSI_CTL), 2, &msiCtl);
vecAddr = (UINT32)pDynaVec->vecAddr;
vxbPciBusCfgWrite (pDev, (UINT32)(msiOffset + PCI_MSI_ADDR_LO), 4,
&(vecAddr));
vxbPciBusCfgWrite (pDev, (UINT32)(msiOffset + PCI_MSI_DATA_32), 2,&vecVal);
寫08寄存器
}
}
實現體 ：vxbPci.bc
讀PCI 配置空間
IMPORT STATUS vxbPciBusCfgRead
(
VXB_DEVICE_ID pDev, /* device info */
UINT32 byteOffset, /* offset into cfg space */
UINT32 transactionSize, /* transaction size */
void * pDataBuf /* buffer to read/write */
)
{
->VXB_PCI_BUS_CFG_READ_INTERNAL(pDev, byteOffset,transactionSize,
pDataBuf)->無法找到下一級具體的實現函數
}
1.5內核提供的讀取\設置配置空間的接口
路徑 ： target/h/hwif/vxbPciLib.h
IMPORT STATUS vxbPciConfigInByte
(
VXB_DEVICE_ID busCtrlID,
int busNo, /* bus number */
int deviceNo, /* device number */
int funcNo, /* function number */
int offset, /* offset into the configuration space */
UINT8 * pData /* data read from the offset */
);
IMPORT STATUS vxbPciConfigInWord
(
VXB_DEVICE_ID busCtrlID,
int busNo, /* bus number */
int deviceNo, /* device number */
int funcNo, /* function number */
int offset, /* offset into the configuration space */
UINT16 * pData /* data read from the offset */
);
IMPORT STATUS vxbPciConfigInLong
(
VXB_DEVICE_ID busCtrlID,
int busNo, /* bus number */
int deviceNo, /* device number */
int funcNo, /* function number */
int offset, /* offset into the configuration space */
UINT32 * pData /* data read from the offset */
);
IMPORT STATUS vxbPciConfigOutByte
(
VXB_DEVICE_ID busCtrlID,
int busNo, /* bus number */
int deviceNo, /* device number */
int funcNo, /* function number */
int offset, /* offset into the configuration space */
UINT8 data /* data written to the offset */
);
IMPORT STATUS vxbPciConfigOutWord
(
VXB_DEVICE_ID busCtrlID,
int busNo, /* bus number */
int deviceNo, /* device number */
int funcNo, /* function number */
int offset, /* offset into the configuration space */
UINT16 data /* data written to the offset */
);
IMPORT STATUS vxbPciConfigOutLong
(
VXB_DEVICE_ID busCtrlID,
int busNo, /* bus number */
int deviceNo, /* device number */
int funcNo, /* function number */
int offset, /* offset into the configuration space */
UINT32 data /* data written to the offset */
);
1.6驅動初始化過程
1.6.1第一步
pexInstInit
{
分配drvctrl、pexConfig、pexIntInfo 空間（hwMemAlloc）
Pcie橋初始化pexBridgeInit
==>讀鏈路狀態寄存器PEX_CFG_LTSSM
===>爲橋配置LAW （這個貌似很關鍵，以前忽略）當前BSP並沒有配置lawBase 和lawSize
===>從pcie配置表中獲取mem memio io 的地址和大小分配配置到 outbound 寄存器
===>處理MSI inbound window
中斷庫初始化vxbPciIntLibInit
==> 申請中斷鏈表(雙向鏈表)空間，並初始化
聲明有pcie設備vxbBusAnnounce
自動配置PCIE vxbPciAutoConfig
總線初始化vxbPciBusTypeInit
寫04寄存器，確保master enable
pexMethodDevCfgWrite (pDev, &pciDev, PCI_CFG_COMMAND, 2,
PCI_CMD_MASTER_ENABLE);
}
1.6.2第二步
pexInstInit2
{
設置初始化完成標記
}
以當前設備橋子設備爲例
PCI_Bus @ 0x004e8bb8 with bridge @ 0x004d98f8
Device Instances
fpgaMdio unit 0 on PCI_Bus @ 0x004e9ff8
BAR1 @ 0xffd10600 (memory mapped)
BAR9 @ 0x00000000 (special)
pDrvCtrl @ 0x00000000
fpgaMdio unit 1 on PCI_Bus @ 0x004ea0f8
BAR1 @ 0xffd10600 (memory mapped)
BAR9 @ 0x00000001 (special)
pDrvCtrl @ 0x00000000
fpgaMdio unit 2 on PCI_Bus @ 0x004ea1f8
BAR1 @ 0xffd10600 (memory mapped)
BAR9 @ 0x00000002 (special)
pDrvCtrl @ 0x00000000
fpgaMdio unit 3 on PCI_Bus @ 0x004ea2f8
BAR1 @ 0xffd10600 (memory mapped)
BAR9 @ 0x00000003 (special)
pDrvCtrl @ 0x00000000
sfpI2c unit 0 on PCI_Bus @ 0x004ea3f8
BAR0 @ 0xffd10610 (memory mapped)
BAR1 @ 0x00000000 (special)
pDrvCtrl @ 0x00000000
sfpI2c unit 1 on PCI_Bus @ 0x004ea4f8
BAR0 @ 0xffd10610 (memory mapped)
BAR1 @ 0x00000001 (special)
pDrvCtrl @ 0x00000000
sfpI2c unit 2 on PCI_Bus @ 0x004ea5f8
BAR0 @ 0xffd10610 (memory mapped)
BAR1 @ 0x00000002 (special)
pDrvCtrl @ 0x00000000
sfpI2c unit 3 on PCI_Bus @ 0x004ea6f8
BAR0 @ 0xffd10610 (memory mapped)
BAR1 @ 0x00000003 (special)
pDrvCtrl @ 0x00000000
vxb8037Sfp unit 0 on PCI_Bus @ 0x004ea7f8
BAR0 @ 0xffd10618 (memory mapped)
BAR1 @ 0x00000004 (special)
pDrvCtrl @ 0x00000000
sfpSensor unit 0 on PCI_Bus @ 0x004ea8f8
pDrvCtrl @ 0x05252cf0
miiBus unit 1 on PCI_Bus @ 0x004eacf8 with busInfo 0x004e95f8
pDrvCtrl @ 0x05016990
miiBus unit 2 on PCI_Bus @ 0x004eaef8 with busInfo 0x004e9638
pDrvCtrl @ 0x05017260
miiBus unit 3 on PCI_Bus @ 0x004eb0f8 with busInfo 0x004e96f8
pDrvCtrl @ 0x04cafb50
miiBus unit 4 on PCI_Bus @ 0x004eb2f8 with busInfo 0x004e9738
pDrvCtrl @ 0x04cf2740
miiBus unit 5 on PCI_Bus @ 0x004eb3f8 with busInfo 0x004e9778
pDrvCtrl @ 0x04cf2cc0
- 橋驅動分析xxxxxBrg.cpp
主要完成工作：
- PCIE設備匹配(根據廠商ID和設備ID匹配)
- MSI中斷申請
UINT nReqNum = 1;
while(nReqNum<FPGA_MSI_NUM)
nReqNum <<= 1;
int iMsiCnt = vxbIntAlloc(pDev, VXB_INT_PCI_MSI, nReqNum); // 最後一個參數必須是2^N
if (iMsiCnt<(int)FPGA_MSI_NUM)
{
DBG_LOG("%s%d: error @ %d\n", pDev->pName, pDev->unitNumber, __LINE__, 0, 0,0);
break;
}
- vxbPci.c
路徑：xxxx/vxw/src/util/vxbPci.c
這裏提供的接口，所有的busCtrlId 設備指的是EPIC控制器QorIQPciEx
STATUS vxbPciConfigForeachFunc
(
VXB_DEVICE_ID busCtrlID,
UINT8 bus, /* bus to start on */
BOOL recurse, /* if TRUE, do subordinate busses */
VXB_PCI_FOREACH_FUNC funcCheckRtn, /* routine to call for each PCI func */
void *pArg /* argument to funcCheckRtn */
)
告訴PCI總線上，這裏有一個PCI 設備
STATUS pciDeviceAnnounce
(
VXB_DEVICE_ID busCtrlID,
UINT8 bus, /* PCI bus number */
UINT8 dev, /* PCI device number */
UINT8 func, /* PCI function number */
void * pArg /* pDev */
)
{
申請空間 struct vxbPciDevice *pPciDev;
獲取中斷控制方法
獲取PCI 配置pPciDev->pPciConfig
獲取中斷信息 pPciDev->pIntInfo
初始化該PCI設備
{
pPciDev->pciBus = bus;
pPciDev->pciDev = dev;
pPciDev->pciFunc = func;
pDev->pNext = NULL;
pDev->pParentBus = p->pDev->u.pSubordinateBus;
pDev->u.pSubordinateBus = NULL;
pDev->busID = VXB_BUSID_PCI;
pDev->pBusSpecificDevInfo = (void *)pPciDev;
pDev->pIntrInfo = NULL;
pDev->pName = NULL;
pDev->pDriver = NULL;
pDev->pDrvCtrl = NULL;
pPciDev->devID = pDev;
}
VxbDevAccessAnnounce
讀配置空間設備ID和廠商ID
如果爲全0xffff，表示沒找到任何設備，否則進入下一步
讀PCI_CFG_HEADER_TYPE獲取頭部類型
{
Bar個數判斷
{
PCI-PCI BRIDGE ->2個bar
PCI-CARD-BUS -> 1個bar
否則有六個bar
}
}
讀配置空間BAR0-BAR5 獲取對應的地址
設置地址爲可編程模式
{
/* set address program mode */
vxbPciBusCfgWrite (pDev, PCI_CFG_BASE_ADDRESS_0 + (4*i),
4, &pciSize);
/* fetch address size value */
vxbPciBusCfgRead (pDev, PCI_CFG_BASE_ADDRESS_0 + (4*i),
4, &pciSize);
/* restore current value */
vxbPciBusCfgWrite (pDev, PCI_CFG_BASE_ADDRESS_0 + (4*i),
4, &(pBaseAddr[i]));
}
保存相應地址到pDev->regBase
pDev->pRegBase[i] = (void *)regBaseTemp;
設置PCI_CFG_COMMAND
{
command = PCI_CMD_IO_ENABLE|PCI_CMD_MEM_ENABLE|PCI_CMD_MASTER_ENABLE;
從代碼執行來看，這裏永遠使能了IO ,MEM 和MASTER
vxbPciBusCfgWrite (pDev, PCI_CFG_COMMAND, 2, &command);
}
}
- vxbPci.bc解析
這個文件很特別，用搜索的方式都不一定能看到，因爲是.bc文件。
路徑 ：target/config/comps/src/hwif/vxbPci.bc
摘自文檔：
NOTE: In VxWorks 6.7 and later, some of the utilities are located in:
installDir/vxworks-6.x/target/config/comps/src/hwif/vxbPci.bc
This file is included (by #include) in VxWorks image project (VIP) builds when the
INCLUDE_PCI_BUS component is added. For BSP command-line builds, the
contents of the file are re-directed to the following file:
調試此文件的方法：
#ifdef DOC
#define INCLUDE_PCI_BUS
#define INCLUDE_PCI_BUS_AUTOCONF
#define INCLUDE_PCI_BUS_SHOW
#include "../config/comps/src/hwif/vxbPci.bc"
#endif /* DOC */
用途：
- 提供配置空間的讀寫接口
- 提供PCI自動控制的處理 INCLUDE_PCI_BUS_AUTOCONF(該組件會被勾選)
- 實現幾個重要的show函數
- PCI自動配置過程
- PCIE總線驅動支持
需勾選下述組件，
問題 ：如果沒有勾選自動配置會是什麼結果？
PCIE控制器初始化和配置在第七章講述Bus Controller Drivers
MSI中斷的標準處理
摘自文檔vxbus_device_driver_developers_guide_6.9.pdf
- 中斷申請及綁定
uVecType is VXB_INT_PCI_MSIX or VXB_INT_PCI_MSI
if ((getCnt = vxbIntAlloc (pDev, uVecType, reqCount)) < reqCount)
{
if (getCnt > 0)
vxbIntFree (pDev);
/*
* If this does not get enough vectors, you can free or continue to use getCnt
* to connect. The connect must be continuous. For example, if you expect to
* allocate 4 interrupts but only acquire 2. You can only connect the 0,1 index
* interrupt. Connecting the 2,3 index is not allowed.
*/
return ERROR;
}
for (uIndex = 0; uIndex < reqCount; uIndex ++)
{
if (vxbIntConnect (pDev, uIndex, isr[uIndex], pArg[uIndex]) != OK)
return ERROR;
}
for (uIndex = 0; uIndex < reqCount; uIndex ++)
{
if (vxbIntEnable (pDev, uIndex, isr[uIndex],pArg[uIndex] != OK)
return ERROR;
}
The following is an example of how to release interrupt resources:
for (uIndex = 0; uIndex < reqCount; uIndex ++)
{
if (vxbIntDisable (pDev, uIndex, isr[uIndex],pArg[uIndex] != OK)
return ERROR;
}
for (uIndex = 0; uIndex < reqCount; uIndex ++)
{
if (vxbIntDisConnect (pDev, uIndex, isr[uIndex], pArg[uIndex]) != OK)
return ERROR;
}
vxbInteFree(pDev);
- 另一種MSI 中斷處理方法 Hwconfig 配置
For example, in order to specify that the PCI network device yn0 output 0 should
use a dynamically generated vector, the following line is included in the table
specified with the input resource.
{ VXB_INTR_DYNAMIC, "yn", 0, 0 }
//實際我司並沒有這麼處理 ，hwconfig搜索不到 VXB_INTR_DYNAMIC 字段
因爲使用的是第一種方式
#ifdef INCLUDE_INTCTLR_DYNAMIC_LIB
{ "msiEnable", HCF_RES_INT, { (void *)TRUE } }
#endif /* INCLUDEINTCTLRDYNAMICLIB */
如果使用第二種方式，就要使用下述API來綁定和使能中斷
vxbIntDynaConnect
vxbMsiConnect
vxbPciMSIProgram 寫MSI中斷
- PCIE總線驅動實例
1. Allocate the per-instance data area used by the driver.
pDrvCtrl = hwMemAlloc (sizeof(*pDrvCtrl));
2. Query required resources from the BSP, and store them locally.
devResourceGet(pHcf, "maxBusSet",
HCF_RES_INT, (void *)&pDrvCtrl->pciMaxBus);
/* etc. */
3. Initialize the PCI interrupt handling information.
vxbPciIntLibInit (pDrvCtrl->pIntInfo);
4. Initialize the support library used for PCI configuration handling.
vxbPciConfigLibInit(pDrvCtrl->pPciConfig, /*…*/ );
5. Initialize the bus controller hardware itself.
g64120aPciBridgeInit (pInst);
6. Inform VxBus about the availability of the new bus.
vxbBusAnnounce (pInst, VXB_BUSID_PCI);
7. If the BSP has requested PCI autoconfiguration, perform the autoconfigure
now.
if (pDrvCtrl->autoConfig)
vxbPciAutoConfig(pInst);
8. Complete VxBus initialization.
vxbPciBusTypeInit (pInst);
7.附錄
7.1配置空間寄存器定義
Target/h/drv/pci/pciConfigLib.h
/* Standard device Type 0 configuration register offsets */
/* Note that only modulo-4 addresses are written to the address register */
#define PCI_CFG_VENDOR_ID 0x00
#define PCI_CFG_DEVICE_ID 0x02
#define PCI_CFG_COMMAND 0x04
#define PCI_CFG_STATUS 0x06
#define PCI_CFG_REVISION 0x08
#define PCI_CFG_PROGRAMMING_IF 0x09
#define PCI_CFG_SUBCLASS 0x0a
#define PCI_CFG_CLASS 0x0b
#define PCI_CFG_CACHE_LINE_SIZE 0x0c
#define PCI_CFG_LATENCY_TIMER 0x0d
#define PCI_CFG_HEADER_TYPE 0x0e
#define PCI_CFG_BIST 0x0f
#define PCI_CFG_BASE_ADDRESS_0 0x10
#define PCI_CFG_BASE_ADDRESS_1 0x14
#define PCI_CFG_BASE_ADDRESS_2 0x18
#define PCI_CFG_BASE_ADDRESS_3 0x1c
#define PCI_CFG_BASE_ADDRESS_4 0x20
#define PCI_CFG_BASE_ADDRESS_5 0x24
#define PCI_CFG_CIS 0x28
#define PCI_CFG_SUB_VENDER_ID 0x2c
#define PCI_CFG_SUB_SYSTEM_ID 0x2e
#define PCI_CFG_EXPANSION_ROM 0x30
#define PCI_CFG_CAP_PTR 0x34
#define PCI_CFG_RESERVED_0 0x35
#define PCI_CFG_RESERVED_1 0x38
#define PCI_CFG_DEV_INT_LINE 0x3c
#define PCI_CFG_DEV_INT_PIN 0x3d
#define PCI_CFG_MIN_GRANT 0x3e
#define PCI_CFG_MAX_LATENCY 0x3f
#define PCI_CFG_SPECIAL_USE 0x41
#define PCI_CFG_MODE 0x43
7.2 PCIE 控制器drv_ctl
typedef struct pex_drv_ctrl
{
VXB_DEVICE_ID pexDev;
void * pexBar;
void * pexHandle;
void * ccsrBar;
BOOL pexAutoConfig;
BOOL pexMsi;
int pexNum;
BOOL pexInitialized;
UINT32 mem32Addr; /* prefetchable */
UINT32 memIo32Addr; /* non-prefetchable */
UINT32 io32Addr;
UINT32 io16Addr;
struct vxbPciConfig * pexConfig;
struct vxbPciInt * pexIntInfo;
int pexMaxBus;
spinlockIsr_t pexLock;
} PEX_DRV_CTRL;
調試PCIE時使用的幾個常用命令：
-> vxbPciHeaderShow 0x20056550
vendor ID = 0x1957
device ID = 0x0825
command register = 0x0007
status register = 0x0010
revision ID = 0x11
class code = 0x0b
sub class code = 0x20
programming interface = 0x00
cache line = 0x10
latency time = 0x00
header type = 0x01
BIST = 0x00
base address 0 = 0x00000000
base address 1 = 0x00000000
primary bus number = 0x00
secondary bus number = 0x01
subordinate bus number = 0x06
secondary latency timer = 0x00
IO base = 0xf1
IO limit = 0x01
secondary status = 0x2000
memory base = 0x8000
memory limit = 0x8070
prefetch memory base = 0xfff1
prefetch memory limit = 0x0001
prefetch memory base upper = 0x00000000
prefetch memory limit upper = 0x00000000
IO base upper 16 bits = 0xffff
IO limit upper 16 bits = 0x000f
expansion ROM base address = 0x00000000
interrupt line = 0x00
interrupt pin = 0x00
bridge control = 0x0000
Capabilities - Power Management
Capabilities - PCIe: Root Port, IRQ 0
Device: Max Payload: 256 bytes, Extended Tag: 5-bit
Acceptable Latency: L0 - <64ns, L1 - <1us
Errors Enabled: Relaxed Ordering No Snoop
Max Read Request 512 bytes
Link: MAX Speed - 5.0Gb/s, MAX Width - by 4 Port - 0 ASPM - L0s
Latency: L0s - <2us, L1 - >64us
ASPM - Disabled, RCB - 128bytes
Speed - 2.5Gb/s, Width - by 1
Root Control Enabled:
Ext Capabilities - Advanced Error Reporting. 0x100. Version 1. AER Control: 0xa0
Uncorrectable : Mask 0x0. Severity 0x62010
Uncorrectable Status: Correctable : Mask 0x2000.
Correctable Status:
HeaderLog:
Error Source Identification: 0x0 0x0
value = 0 = 0x0
->
-> vxbPciTopoShow 0x20056550
[0,0,0] - (1957 0825) type=PROCESSOR
status=0x0010 ( CAP DEVSEL=0 )
command=0x0007 ( IO_ENABLE MEM_ENABLE MASTER_ENABLE )
[1,0,0] - (111d 803c) type=P2P BRIDGE to [2,0,0]
base/limit:
mem= 0x80000000/0x807fffff
preMem=0x00000000fff00000/0x00000000000fffff
I/O= 0xfffff000/0x000f0fff
status=0x0010 ( CAP DEVSEL=0 )
command=0x0007 ( IO_ENABLE MEM_ENABLE MASTER_ENABLE )
[2,2,0] - (111d 803c) type=P2P BRIDGE to [3,0,0]
base/limit:
mem= 0xfff00000/0x000fffff
preMem=0x00000000fff00000/0x00000000000fffff
I/O= 0xfffff000/0x000f0fff
status=0x0010 ( CAP DEVSEL=0 )
command=0x0007 ( IO_ENABLE MEM_ENABLE MASTER_ENABLE )
[2,3,0] - (111d 803c) type=P2P BRIDGE to [4,0,0]
base/limit:
mem= 0xfff00000/0x000fffff
preMem=0x00000000fff00000/0x00000000000fffff
I/O= 0xfffff000/0x000f0fff
status=0x0010 ( CAP DEVSEL=0 )
command=0x0007 ( IO_ENABLE MEM_ENABLE MASTER_ENABLE )
[2,4,0] - (111d 803c) type=P2P BRIDGE to [5,0,0]
base/limit:
mem= 0xfff00000/0x000fffff
preMem=0x00000000fff00000/0x00000000000fffff
I/O= 0xfffff000/0x000f0fff
status=0x0010 ( CAP DEVSEL=0 )
command=0x0007 ( IO_ENABLE MEM_ENABLE MASTER_ENABLE )
[2,5,0] - (111d 803c) type=P2P BRIDGE to [6,0,0]
base/limit:
mem= 0x80000000/0x805fffff
preMem=0x00000000fff00000/0x00000000000fffff
I/O= 0xfffff000/0x000f0fff
status=0x0010 ( CAP DEVSEL=0 )
command=0x0007 ( IO_ENABLE MEM_ENABLE MASTER_ENABLE )
[6,0,0] - (595a 0037) type=OTHER DEVICE
status=0x0010 ( CAP DEVSEL=0 )
command=0x0007 ( IO_ENABLE MEM_ENABLE MASTER_ENABLE )
bar0 in 32-bit mem space @ 0x80000000
bar1 in 32-bit mem space @ 0x80400000
value = 65535 = 0xffff