在xilinx模板中,存在一個Aurora樣本工程,包含衆多的子函數,本系列本文將逐一對其進行解析,首先是aurora_8b10b_0_FRAME_GEN函數,根據官方的說明,其作用是:該模塊是一個模式生成器,用於在硬件上測試激光設計。它生成數據並將其通過激光通道。如果連接到幀接口,它將生成不同大小和間隔的幀。LFSR用於產生僞隨機數據,LFSR的低位連接到REM總線。
REM在此處的含義應該是remaining,其輸出接到下一個模塊的LL_IP_REM接口,根據其數值令TKKP爲10 or 11,是的產後是呢過的數據更加隨機。
1、復位管理模塊
//*********************************Main Body of Code********************************** always @ (posedge USER_CLK) begin if(RESET) channel_up_cnt <= `DLY 5'd0; else if(CHANNEL_UP) if(&channel_up_cnt) channel_up_cnt <= `DLY channel_up_cnt; else channel_up_cnt <= `DLY channel_up_cnt + 1'b1; else channel_up_cnt <= `DLY 5'd0; end assign dly_data_xfer = (&channel_up_cnt); //Generate RESET signal when Aurora channel is not ready assign reset_c = RESET || !dly_data_xfer;
RESET爲模塊復位輸入信號,除此之外,aurora ip還會產生一個channel_up信號輸出,該信號額官方含義爲:Asserted when Aurora 8B/10B channel initialization is complete and the channel is ready for data transfer. tx_channel_up and rx_channel_up are only applicable to their respective simplex cores.,也就是當Aurora 8B/10B通道初始化完成且通道準備好進行數據傳輸時置一CHANNEL_UP。
當channel_up延時等待16個時鐘,&channel_up_cnt表示各個位相與,即各個位爲1,故此處就是讓幀數據生成單元延時復位操作。
2、生成隨機數據模塊
就是一個LFSR(linear feedback shift register,線性反饋移位寄存器),生成有顧慮的隨機數
//______________________________ Transmit Data __________________________________ //Generate random data using XNOR feedback LFSR always @(posedge USER_CLK) if(reset_c) begin data_lfsr_r <= `DLY 16'hABCD; //random seed value end else if(!TX_DST_RDY_N && !idle_r) begin data_lfsr_r <= `DLY {!{data_lfsr_r[3]^data_lfsr_r[12]^data_lfsr_r[14]^data_lfsr_r[15]}, data_lfsr_r[0:14]}; end
其仿真(modelsim)結果爲
3、幀數據計數器與發送數據個數計數器
官方架構中使用了兩個always塊,一個always塊產生每一幀數據發送的最大數據個數,然後另一個always塊計數已發送的數據個數,當兩個計數器的數值相等時代表一幀數據發送完畢。
代碼:
//Use a counter to determine the size of the next frame to send always @(posedge USER_CLK) if(reset_c) frame_size_r <= `DLY 8'h00; else if(single_cycle_frame_r || eof_r) frame_size_r <= `DLY frame_size_r + 1; //Use a second counter to determine how many bytes of the frame have already been sent always @(posedge USER_CLK) if(reset_c) bytes_sent_r <= `DLY 8'h00; else if(sof_r) bytes_sent_r <= `DLY 8'h01; else if(!TX_DST_RDY_N && !idle_r) bytes_sent_r <= `DLY bytes_sent_r + 1;
此外,在數據的傳輸過程中,使用計數器產生一個ifg_size_r,使得ifg_size_c每個15個時鐘產生一個時鐘的高電平,這個信號控制個控制值信號的刷新頻率。(個人理解)
//Use a freerunning counter to determine the IFG always @(posedge USER_CLK) if(reset_c) ifg_size_r <= `DLY 4'h0; else ifg_size_r <= `DLY ifg_size_r + 1; //IFG is done when ifg_size register is 0 assign ifg_done_c = (ifg_size_r == 4'h0);
4、獨熱碼狀態機
本always塊控制着狀態的轉移,狀態輸出信號控制這信號的發送(主要是生成了Tlast和Tvalid信號)
//State registers for 1-hot state machine always @(posedge USER_CLK) if(reset_c) begin idle_r <= `DLY 1'b1; single_cycle_frame_r <= `DLY 1'b0; sof_r <= `DLY 1'b0; data_cycle_r <= `DLY 1'b0; eof_r <= `DLY 1'b0; end else if(!TX_DST_RDY_N) begin idle_r <= `DLY next_idle_c; single_cycle_frame_r <= `DLY next_single_cycle_frame_c; sof_r <= `DLY next_sof_c; data_cycle_r <= `DLY next_data_cycle_c; eof_r <= `DLY next_eof_c; end
idle_r=0表示空閒狀態,不進行數據傳輸,idle=0表示一幀數據,single_cycle_frame_r表示一幀新的數據準備好開始傳輸,sof_r表示開始一幀數據的開始,data_cycyle_r表示正在進行數據傳輸,eof_r表示數據傳輸結束。
//Nextstate logic for 1-hot state machine assign next_idle_c = !ifg_done_c && (single_cycle_frame_r || eof_r || idle_r); assign next_single_cycle_frame_c = (ifg_done_c && (frame_size_r == 0)) && (idle_r || single_cycle_frame_r || eof_r); assign next_sof_c = (ifg_done_c && (frame_size_r != 0)) && (idle_r || single_cycle_frame_r || eof_r); assign next_data_cycle_c = (frame_size_r != bytes_sent_r) && (sof_r || data_cycle_r); assign next_eof_c = (frame_size_r == bytes_sent_r) && (sof_r || data_cycle_r);
使用杜熱碼的形式進行狀態機切換,根據所處狀態生成last和valid信號