對於imx53中的gpio操作一直概念不清楚，最近火大，直接把gpio.c註釋一下，該代碼位於arch\arm\plat-mxc\gpio.c中
對於gpio的讀寫操作網上有一篇關於imx51的介紹已經很不錯了，這裏我的重點是gpio的中斷，尤其是中斷共享
一、mx53/mx51 GPIO 操作原理
（一）GPIO 寄存器
每組GPIO有8個寄存器：
1. DR： Data Register
當GDIR設置爲輸出時, 寫DR的內容用來驅動GPIO的pins，讀DR的內容則返
回存儲在DR中的值
當GDIR設置爲輸入時，讀DR返回給定IO pin的狀態(PSR data)，而不是DR
data
2. GDIR: Data Direction Register
控制GPIO pins的方向， 1作爲輸出，0作爲輸入，寄存器中的每一位標識一
個特定pad的方向。 僅當相應的pins被設置爲GPIO，GDIR才起作用
3. PSR：Pad Sample Register
32-bit的只讀寄存器。寄存器中的每一位都存儲相應pad的值
4. ICR1， ICR2： 中斷觸發方式控制寄存器 用於設置中斷觸發方式
兩個32-bit寄存器， 寄存器中每兩位控制一條中斷線，ICR1控制中斷0~15,
ICR2控制中斷16～31
00中斷是low-level觸發
01中斷是high-level觸發
10中斷是rise-edge觸發
11中斷時fall-edge觸發
5. IMR： Interrupt Mask Register 中斷使能寄存器 用於控制中斷的使能，總共有32位，對應32箇中斷
32bit register. 每一位是相應中斷線的屏蔽位， 0中斷被屏蔽，1中斷被使
能
6. ISR： Interrupt Status Register 中斷狀態寄存器，用於查詢對應的32個引腳的哪一位觸發的中斷，默認沒有中斷觸發時是1，當觸發的時候爲0
32bit register, 每一位用於指定對應的中斷線是否有中斷髮生，當一箇中斷
發生，這個寄存器中的相應位被設置
7. EDGE_SEL：Edge Select Register 設置爲邊緣觸發的寄存器，感覺和icr重了，沒有必要用了，有點多餘，個人觀點哈，呵呵
32bit 寄存器，覆蓋ICR寄存器的配置，選擇edge 作爲中斷觸發的條件
/*
* MXC GPIO support. (c) 2008 Daniel Mack <[email protected]>* Copyright 2008 Juergen Beisert, [email protected]
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/sysdev.h>
#include <mach/hardware.h>
#include <asm-generic/bug.h>
static struct mxc_gpio_port *mxc_gpio_ports;
static int gpio_table_size;
#define cpu_is_mx1_mx2() (cpu_is_mx1() || cpu_is_mx2())
#define GPIO_DR (cpu_is_mx1_mx2() ? 0x1c : 0x00)
#define GPIO_GDIR (cpu_is_mx1_mx2() ? 0x00 : 0x04)
#define GPIO_PSR (cpu_is_mx1_mx2() ? 0x24 : 0x08)
#define GPIO_ICR1 (cpu_is_mx1_mx2() ? 0x28 : 0x0C)
#define GPIO_ICR2 (cpu_is_mx1_mx2() ? 0x2C : 0x10)
#define GPIO_IMR (cpu_is_mx1_mx2() ? 0x30 : 0x14)
#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18)
#define GPIO_INT_LOW_LEV (cpu_is_mx1_mx2() ? 0x3 : 0x0)
#define GPIO_INT_HIGH_LEV (cpu_is_mx1_mx2() ? 0x2 : 0x1)
#define GPIO_INT_RISE_EDGE (cpu_is_mx1_mx2() ? 0x0 : 0x2)
#define GPIO_INT_FALL_EDGE (cpu_is_mx1_mx2() ? 0x1 : 0x3)
#define GPIO_INT_NONE 0x4
/* Note: This driver assumes 32 GPIOs are handled in one register */
//清除gpio口的中斷狀態寄存器；
static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index)//清除gpio口的狀態
{
__raw_writel(1 << index, port->base + GPIO_ISR);//將相應的位清除，爲1是說明沒有觸發
}
//設置gpio口相應的口的中斷使能，index爲第port組gpio口的第幾個口
static void _set_gpio_irqenable(struct mxc_gpio_port *port, u32 index,
int enable)
{
u32 l;
l = __raw_readl(port->base + GPIO_IMR);//獲取當前中斷控制寄存器狀態
l = (l & (~(1 << index))) | (!!enable << index);//將相應gpio口的imr置位。1使能， (!!enable << index)這句不知道什麼意思
__raw_writel(l, port->base + GPIO_IMR);//寫入相應的狀態到imr
}
//清除中斷號對應的狀態以接收下一個中斷，從而達到響應中斷的目的。
static void gpio_ack_irq(u32 irq)
{
u32 gpio = irq_to_gpio(irq);//獲取當前gpio口的基地址
_clear_gpio_irqstatus(&mxc_gpio_ports[gpio / 32], gpio & 0x1f);//與0x1f與，爲了取32位
}
//屏蔽中斷號對應的中斷
static void gpio_mask_irq(u32 irq)
{
u32 gpio = irq_to_gpio(irq);
_set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 0);
}
//開啓中斷號對應的中斷
static void gpio_unmask_irq(u32 irq)
{
u32 gpio = irq_to_gpio(irq);
_set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 1);
}
static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset);
//設置中斷響應類型
static int gpio_set_irq_type(u32 irq, u32 type)
{
u32 gpio = irq_to_gpio(irq);
struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
u32 bit, val;
int edge;
void __iomem *reg = port->base;
port->both_edges &= ~(1 << (gpio & 31));
switch (type) {
case IRQ_TYPE_EDGE_RISING://上升沿觸發
edge = GPIO_INT_RISE_EDGE;
break;
case IRQ_TYPE_EDGE_FALLING:
edge = GPIO_INT_FALL_EDGE;
break;
case IRQ_TYPE_EDGE_BOTH:
val = mxc_gpio_get(&port->chip, gpio & 31);//獲取當前gpio的值，屬於前16還是後16
if (val) {
edge = GPIO_INT_LOW_LEV;
pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
} else {
edge = GPIO_INT_HIGH_LEV;
pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
}
port->both_edges |= 1 << (gpio & 31);
break;
case IRQ_TYPE_LEVEL_LOW://低電平觸發
edge = GPIO_INT_LOW_LEV;
break;
case IRQ_TYPE_LEVEL_HIGH:
edge = GPIO_INT_HIGH_LEV;
break;
default:
return -EINVAL;
}
/* set the correct irq handler */
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))//電平觸發方式
__set_irq_handler_unlocked(irq, handle_level_irq);
else if (type & IRQ_TYPE_EDGE_BOTH)
__set_irq_handler_unlocked(irq, handle_edge_irq);
/*這裏非常有玄機，可以同時設置高位和地位的icr寄存器，即icr1 icr2 比如當gpio爲低16爲的時候，這時候((gpio & 0x10) >> 2)爲0 與0x10與是爲了判斷是不是高於16位，*/
/*當高於16位時，此時與0x10與 取0b00010000，然後右移2位，爲0b00000100 即爲4 這時 GPIO_ICR1+4= GPIO_ICR2*/
reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
bit = gpio & 0xf;//取低四位
/*先將寄存器中對應的兩位清零，因爲兩位控制一個gpio觸發狀態，所以*/
/*先bit<<1,相當於乘以2，然後將0x3移位，然後反向，比如gpio5-5，先將gpio後四位即bit=5右移2位，爲10 然*/
/*然後0x3右移10位，位0x110000000000 然後反向爲0x001111111111 然後與val與，使gpio對應的位清零以防止設置的時候出錯*/
val = __raw_readl(reg) & ~(0x3 << (bit << 1));
__raw_writel(val | (edge << (bit << 1)), reg);/*對於gpio5-5將edge右移10位，設置ICR*/
_clear_gpio_irqstatus(port, gpio & 0x1f);//清除中斷寄存器狀態
return 0;
}
//中斷觸發方式高電平觸發和低電平觸發轉換
static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
{
void __iomem *reg = port->base;
u32 bit, val;
int edge;
reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
bit = gpio & 0xf;
val = __raw_readl(reg);
edge = (val >> (bit << 1)) & 3;
val &= ~(0x3 << (bit << 1));
if (edge == GPIO_INT_HIGH_LEV) {
edge = GPIO_INT_LOW_LEV;
pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
} else if (edge == GPIO_INT_LOW_LEV) {
edge = GPIO_INT_HIGH_LEV;
pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
} else {
pr_err("mxc: invalid configuration for GPIO %d: %x\n",
gpio, edge);
return;
}
__raw_writel(val | (edge << (bit << 1)), reg);
}
/* handle 32 interrupts in one status register */
static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
{
u32 gpio_irq_no_base = port->virtual_irq_start;
while (irq_stat != 0) {
int irqoffset = fls(irq_stat) - 1;
if (port->both_edges & (1 << irqoffset))
mxc_flip_edge(port, irqoffset);
generic_handle_irq(gpio_irq_no_base + irqoffset);
irq_stat &= ~(1 << irqoffset);
}
}
/* MX1 and MX3 has one interrupt *per* gpio port */
static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
{
u32 irq_stat;
u32 mask = 0xFFFFFFFF;
struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq);
if (port->irq_high) {
if (irq == port->irq)
mask = 0x0000FFFF;
else
mask = 0xFFFF0000;
}
irq_stat = __raw_readl(port->base + GPIO_ISR) &
(__raw_readl(port->base + GPIO_IMR) & mask);
mxc_gpio_irq_handler(port, irq_stat);
}
/* MX2 has one interrupt *for all* gpio ports */
static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
{
int i;
u32 irq_msk, irq_stat;
struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq);
/* walk through all interrupt status registers */
for (i = 0; i < gpio_table_size; i++) {
irq_msk = __raw_readl(port[i].base + GPIO_IMR);
if (!irq_msk)
continue;
irq_stat = __raw_readl(port[i].base + GPIO_ISR) & irq_msk;
if (irq_stat)
mxc_gpio_irq_handler(&port[i], irq_stat);
}
}
/*
* Set interrupt number "irq" in the GPIO as a wake-up source.
* While system is running all registered GPIO interrupts need to have
* wake-up enabled. When system is suspended, only selected GPIO interrupts
* need to have wake-up enabled.
* @param irq interrupt source number
* @param enable enable as wake-up if equal to non-zero
* @return This function returns 0 on success.
*/
//
static int gpio_set_wake_irq(u32 irq, u32 enable)
{
u32 gpio = irq_to_gpio(irq);
u32 gpio_idx = gpio & 0x1F;
struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
if (enable) {
port->suspend_wakeup |= (1 << gpio_idx);
if (port->irq_high && (gpio_idx >= 16))
enable_irq_wake(port->irq_high);//使能中斷喚醒功能，這個函數在interrupt.h中定義的
else
enable_irq_wake(port->irq);
} else {
port->suspend_wakeup &= ~(1 << gpio_idx);
if (port->irq_high && (gpio_idx >= 16))
disable_irq_wake(port->irq_high);
else
disable_irq_wake(port->irq);
}
return 0;
}
/*中斷處理函數，這個數組需要註冊到系統 非常重要*/
static struct irq_chip gpio_irq_chip = {
.ack = gpio_ack_irq,
.mask = gpio_mask_irq,
.unmask = gpio_unmask_irq,
.set_type = gpio_set_irq_type,
.set_wake = gpio_set_wake_irq,
};
request_irq
static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
int dir)
{
struct mxc_gpio_port *port =
container_of(chip, struct mxc_gpio_port, chip);
u32 l;
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
l = __raw_readl(port->base + GPIO_GDIR);
if (dir)
l |= 1 << offset;
else
l &= ~(1 << offset);
__raw_writel(l, port->base + GPIO_GDIR);
spin_unlock_irqrestore(&port->lock, flags);
}
static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct mxc_gpio_port *port =
container_of(chip, struct mxc_gpio_port, chip);
void __iomem *reg = port->base + GPIO_DR;
u32 l;
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
l = (__raw_readl(reg) & (~(1 << offset))) | (value << offset);
__raw_writel(l, reg);
spin_unlock_irqrestore(&port->lock, flags);
}
static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct mxc_gpio_port *port =
container_of(chip, struct mxc_gpio_port, chip);
return (__raw_readl(port->base + GPIO_PSR) >> offset) & 1;
}
static int mxc_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
_set_gpio_direction(chip, offset, 0);
return 0;
}
static int mxc_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
mxc_gpio_set(chip, offset, value);
_set_gpio_direction(chip, offset, 1);
return 0;
}
//初始化所有gpio口到系統，是這個文件的核心！！！
int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
{
int i, j;
int ret = 0;
/* save for local usage */
mxc_gpio_ports = port;
gpio_table_size = cnt;
printk(KERN_INFO "MXC GPIO hardware\n");
for (i = 0; i < cnt; i++) {
/* disable the interrupt and clear the status */
__raw_writel(0, port[i].base + GPIO_IMR);/*disable interrupt*/
__raw_writel(~0, port[i].base + GPIO_ISR);//清除中斷狀態寄存器 全部寫1
for (j = port[i].virtual_irq_start;
j < port[i].virtual_irq_start + 32; j++) {
set_irq_chip(j, &gpio_irq_chip);//註冊中斷相關處理函數
set_irq_handler(j, handle_level_irq);
set_irq_flags(j, IRQF_VALID);
}
/* register gpio chip */
port[i].chip.direction_input = mxc_gpio_direction_input;//與本文件的gpio操作綁定，非常重要
port[i].chip.direction_output = mxc_gpio_direction_output;
port[i].chip.get = mxc_gpio_get;
port[i].chip.set = mxc_gpio_set;
port[i].chip.base = i * 32;
port[i].chip.ngpio = 32;
spin_lock_init(&port[i].lock);
/* its a serious configuration bug when it fails */
BUG_ON( gpiochip_add(&port[i].chip) < 0 );
if (!cpu_is_mx2() || cpu_is_mx25()) {
/* setup one handler for each entry */
set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
set_irq_data(port[i].irq, &port[i]);
if (port[i].irq_high) {
set_irq_chained_handler(port[i].irq_high, mx3_gpio_irq_handler);
set_irq_data(port[i].irq_high, &port[i]);
}
}
}
if (cpu_is_mx2()) {
/* setup one handler for all GPIO interrupts */
set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
set_irq_data(port[0].irq, port);
}
return ret;
}
#ifdef CONFIG_PM
/*!
* This function puts the GPIO in low-power mode/state.
* All the interrupts that are enabled are first saved.
* Only those interrupts which registers as a wake source by calling
* enable_irq_wake are enabled. All other interrupts are disabled.
*
* @param dev the system device structure used to give information
* on GPIO to suspend
* @param mesg the power state the device is entering
*
* @return The function always returns 0.
*/
static int mxc_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
{
int i;
struct mxc_gpio_port *port = mxc_gpio_ports;
for (i = 0; i < gpio_table_size; i++) {
void __iomem *isr_reg;
void __iomem *imr_reg;
isr_reg = port[i].base + GPIO_ISR;
imr_reg = port[i].base + GPIO_IMR;
if (__raw_readl(isr_reg) & port[i].suspend_wakeup)
return -EPERM;
port[i].saved_wakeup = __raw_readl(imr_reg);//將當前imr狀態保存，
__raw_writel(port[i].suspend_wakeup, imr_reg);//將掛起的狀態寫入imr
}
return 0;
}
/*!
* This function brings the GPIO back from low-power state.
* All the interrupts enabled before suspension are re-enabled from
* the saved information.
*
* @param dev the system device structure used to give information
* on GPIO to resume
*
* @return The function always returns 0.
*/
static int mxc_gpio_resume(struct sys_device *dev)
{
int i;
struct mxc_gpio_port *port = mxc_gpio_ports;
for (i = 0; i < gpio_table_size; i++) {
void __iomem *isr_reg;
void __iomem *imr_reg;
isr_reg = port[i].base + GPIO_ISR;
imr_reg = port[i].base + GPIO_IMR;
__raw_writel(port[i].saved_wakeup, imr_reg);//將保存的值寫入imr寄存器
}
return 0;
}
#else
#define mxc_gpio_suspend NULL
#define mxc_gpio_resume NULL
#endif /* CONFIG_PM */
/*!
* This structure contains pointers to the power management callback functions.
*/
static struct sysdev_class mxc_gpio_sysclass = {
.name = "mxc_gpio",
.suspend = mxc_gpio_suspend,
.resume = mxc_gpio_resume,
};
/*!
* This structure represents GPIO as a system device.
* System devices follow a slightly different driver model.
* They don't need to do dynammic driver binding, can't be probed,
* and don't reside on any type of peripheral bus.
* So, it is represented and treated a little differently.
*/
static struct sys_device mxc_gpio_device = {
.id = 0,
.cls = &mxc_gpio_sysclass,
};
static int gpio_sysdev_init(void)
{?
int ret = sysdev_class_register(&mxc_gpio_sysclass);
if (ret)
return ret;
return sysdev_register(&mxc_gpio_device);
}
arch_initcall(gpio_sysdev_init);
