module simple_dc_ram#( parameter dw = 64,aw=7) (
input rd_clk,wr_clk,wr,
input [aw-1:0]wr_addr,rd_addr,
output reg [dw-1:0]q ,
input [dw-1:0]d
);
reg [dw-1:0] mem [(1<<aw)-1:0];
always @(posedge rd_clk) q <= mem[rd_addr];
always @(posedge wr_clk) if (wr) mem[wr_addr] <= d;
endmodule
