FPU指令集

FPU指令收集

Data Transfer and Constants

FLD src  Load real: st(0) <- src (mem32/mem64/mem80)

//fld st(2),word ptr [200]:載入數據到寄存器

// fld st(1),dword ptr [200]:word/dword聲明運算的精度

FILD src  Load integer: st(0) <- src (mem16/mem32/mem64)
FBLD src  Load BCD: st(0) <- src (mem80)
FLDZ  Load zero: st(0) <- 0.0
FLD1  Load 1: st(0) <- 1.0
FLDPI  Load pi: st(0) <- n (ie, pi)
FLDL2T  Load log2(10): st(0) <- log2(10)
FLDL2E  Load log2(e): st(0) <- log2(e)
FLDLG2  Load log10(2): st(0) <- log10(2)
FLDLN2  Load loge(2): st(0) <- loge(2)
FST dest  Store real: dest <- st(0) (mem32/mem64)
FSTP dest  dest <- st(0) (mem32/mem64/mem80); pop stack
FIST dest  Store integer: dest <- st(0) (mem32/mem64)
FISTP dest  dest <- st(0) (mem16/mem32/mem64); pop stack
FBST dest  Store BCD: dest <- st(0) (mem80)
FBSTP dest  dest <- st(0) (mem80); pop stack

 

Compare

FCOM  Compare real: Set flags as for st(0) - st(1)
FCOM op  Set flags as for st(0) - op (mem32/mem64)
FCOMP op  Compare st(0) to op (reg/mem); pop stack
FCOMPP  Compare st(0) to st(1); pop stack twice
FICOM op  Compare integer: Set flags as for st(0) - op (mem16/mem32)
FICOMP op  Compare st(0) to op (mem16/mem32); pop stack
FTST  Test for zero: Compare st(0) to 0.0
FUCOM st(i)  Unordered Compare: st(0) to st(i) [486]
FUCOMP st(i)  Compare st(0) to st(i) and pop stack
FUCOMPP st(i)  Compare st(0) to st(i) and pop stack twice
FXAM  Examine: Eyeball st(0) (set condition codes)

 

Arithmetic

FADD  Add real: st(0) <- st(0) + st(1)
FADD src  st(0) <- st(0) + src (mem32/mem64)
FADD st(i),st  st(i) <- st(i) + st(0)
FADDP st(i),st  st(i) <- st(i) + st(0); pop stack
FIADD src  Add integer: st(0) <- st(0) + src (mem16/mem32)
FSUB  Subtract real: st(0) <- st(0) - st(1)
FSUB src  st(0) <- st(0) - src (reg/mem)
FSUB st(i),st  st(i) <- st(i) - st(0)
FSUBP st(i),st  st(i) <- st(i) - st(0); pop stack
FSUBR st(i),st  Subtract Reversed: st(0) <- st(i) - st(0)
FSUBRP st(i),st  st(0) <- st(i) - st(0); pop stack
FISUB src  Subtract integer: st(0) <- st(0) - src (mem16/mem32)
FISUBR src  Subtract Rvrsd int: st(0) <- src - st(0) (mem16/mem32)
FMUL  Multiply real: st(0) <- st(0) * st(1)
FMUL st(i)  st(0) <- st(0) * st(i)
FMUL st(i),st  st(i) <- st(0) * st(i)
FMULP st(i),st  st(i) <- st(0) * st(i); pop stack
FIMUL src  Multiply integer: st(0) <- st(0) * src (mem16/mem32)
FDIV  Divide real: st(0) <- st(0) ÷ st(1)
FDIV st(i)  st(0) <- st(0) ÷ t(i)
FDIV st(i),st  st(i) <- st(0) ÷ st(i)
FDIVP st(i),st  st(i) <- st(0) ÷ st(i); pop stack
FIDIV src  Divide integer: st(0) <- st(0) ÷ src (mem16/mem32)
FDIVR st(i),st  Divide Rvrsd real: st(0) <- st(i) ÷ st(0)
FDIVRP st(i),st  st(0) <- st(i) ÷ st(0); pop stack
FIDIVR src  Divide Rvrsd int: st(0) <- src ÷ st(0) (mem16/mem32)
FSQRT  Square Root: st(0) <- sqrt st(0)
FSCALE  Scale by power of 2: st(0) <- 2 ^ st(0)
FXTRACT  Extract exponent: st(0) <- exponent of st(0); and gets pushed st(0) <- significand of st(0)
FPREM  Partial remainder: st(0) <- st(0) MOD st(1)
FPREM1  Partial Remainder (IEEE): same as FPREM, but in IEEE standard [486]
FRNDINT  Round to nearest int: st(0) <- INT( st(0) ); depends on RC flag
FABS  Get absolute value: st(0) <- ABS( st(0) ); removes sign
FCHS  Change sign: st(0) <- -st(0)

 

Transcendental

FCOS  Cosine: st(0) <- COS( st(0) )
FPTAN  Partial tangent: st(0) <- TAN( st(0) )
FPATAN  Partial Arctangent: st(0) <- ATAN( st(0) )
FSIN  Sine: st(0) <- SIN( st(0) )
FSINCOS  Sine and Cosine: st(0) <- SIN( st(0) ) and is pushed to st(1) st(0) <- COS( st(0) )
F2XM1  Calculate (2 ^ x)-1: st(0) <- (2 ^ st(0)) - 1
FYL2X  Calculate Y * log2(X): st(0) is Y; st(1) is X; this replaces st(0) and st(1) with: st(0) * log2( st(1) )
FYL2XP1  Calculate Y * log2(X+1): st(0) is Y; st(1) is X; this replaces st(0) and st(1) with: st(0) * log2( st(1)+1 )
Processor Control
FINIT  Initialize FPU
FSTSW  AX store Status word: AX <- MSW
FSTSW dest  dest <- MSW (mem16)
FLDCW src  Load control word: FPU CW <- src (mem16)
FSTCW dest  Store control word: dest <- FPU CW
FCLEX  Clear exceptions
FSTENV dest  Store environment: store status, control and tag words and exception pointers into memory at dest
FLDENV src  Load environment: load environment from memory at src
FSAVE dest  Store FPU state: store FPU state into 94-bytes at dest
FRSTOR src  Load FPU state: restore FPU state as saved by FSAVE
FINCSTP  Increment FPU stack ptr: st(6)<-st(5); st(5)<-st(4),...,st(0)<-?
FDECSTP  Decrement FPU stack ptr: st(0)<-st(1); st(1)<-st(2),...,st(7)<-?
FFREE  st(i) Mark reg st(i) as unused
FNOP  No operation: st(0) <- st(0)
WAIT/FWAIT  Synchronize FPU & CPU: Halt CPU until FPU finishes current opcode.

 

FXCH - exchange instruction st(0) <- st(1) st(1) <- st(0)