verilog connection review
1、两个小模块的连接
2、testbench与design连接
systemverilog:
1、*port connection
2、.name connection
disadvantage of verilog module connection:
- declarations must be duplicated in multiple modules
- communication protocols must be duplicated in several modules
- risk of mismatch declaration
- a change in design specifications can require modifications in multiple module
=>interface
<port.name>.<internal_interface_signal_name>(便于多种interface时信号区分)
利用modport可以添加方向信号:
在仿真时避免竞争:
sv testbench in simulation(在时钟沿前采样,在时钟沿后驱动)
clocking block
arbif.cb.request <=1//all drive must use non-blocking assignment
value = arbif.cb.grant//sample use blocking assignment
为了防止冒险情况的发生,分成了多个region(vcs 中有此详细介绍)
time region:
program block
program block:
benefits:
- 将testbench和DUV进行分开
- 通过运行timing region来减小冒险
function:
- 通常在top层例化
- leaf node,no module hierarchy,just class hierarchy
- 只能加initial块,不能加always块
- 隐藏finish函数