Digital signals
The screen already has a few chips mounted on glass alongside the edges of the panel. These are the source and gate drivers, which allow us to address individual pixels of the screen. They are just plain old shift registers coupled with some high-voltage amplifiers.
The basic structure of the digital logic on the panel.
The digital signals consist of two sets:
- Gate driver: U1CE1, U1CE2, U2CE1, U2CE2, U1SPV, U2SPV, U1CKV, U2CKV, GMODE1, GMODE2 and RL.
- Source driver: CL, LE, OE, SPH, SHR, D0-D7.
The gate driver is a bit of a mystery: the multitude of signals apparently allows you to chain the two halfs of the display in different ways. However, it is not really described in any public materials, so I just went and copied the arrangement from the available schematic. Connecting U1SPV & U2SPV, U1CKV & U2CKV and GMODE1 & GMODE2 pairwise together causes the gate driver to neatly advance row-by-row from first half of the display to the second half. For some reason, the chip-enables are connected so that U1CE1 is low and all the others are high.
The source driver is somewhat simpler: the few individual signals are the clock, latch enable, output enable and start pulse for the logic. Basically it is a 2-bit 800-deep shift register followed by a latch. One display row is shifted into the register, loaded onto the latch and then strobed to display using the output enable.
There is nothing special about driving these signals. You can just connect them to whatever IO-pins you have free. Only point of note is that they are all 3.3 V logic level.
Driving waveforms
Having the electrical connections figured out, there is the problem of what kind of signals to feed into the display panel. In theory, it is simple enough: just shift in some bits to the source driver register and step the gate driver register. In practise, however, there are a few gotchas..
At first I had some trouble getting anything to happen. It turned out to be a combination of badly connected cables, wrongly defined pinouts and various bugs. However, the first thing I did manage to get to display is this brute force pattern generated by dumping rand() output into the GPIO pins:
The gate driver is definitely the easier one. Its purpose is to simply select one row of the panel for updating. How this is done is that you shift in a single "1" bit, and then "0" bits every time you want to advance to the next row. The "1" bit will shift through the register until it falls off the far end.
What's funny, though, is that you can actually see this happening:
That video shows the active row driver line visible at the edge of the panel. Apparently the electrophoretic material extends a bit past the actual display area, so that anything that happens in the electrodes underneath becomes visible.
Gate driver waveforms.
Basically, to start a frame, you toggle GMODE (gate output enable) high and activate SPV (start pulse vertical, active low) for one CKV clock cycle. After that you toggle CKV for each row you want to advance. It seems that the gate driver is only on while the CKV is high, and also that the on-off ratio of CKV is important. It seems necessary to have CKV off much longer than it is on, otherwise the image leaks to other rows also. Probably some kind of residual charge which must be allowed to dissipate.
The following table lists the timings that I have found suitable for my panel:
| Purpose | CKV high time | CKV low time |
|---|---|---|
| Frame start/end pulses | 1 µs | 4 µs |
| Write data onto row | 5 µs | 200 µs |
| Skip row without writing | 1 µs | 100 µs |
| Bulk clear | 20 µs | 200 µs |
Source driver
The source driver is not very complex either. You shift in 800 pixels of data, 2 bits per pixel. After all the data is in the shift register, you pulse the latch enable to store it into the latch. Then you pulse the output enable when you want to write out the row.
The SPH signal starts the row register, and should remain low for the duration of the row. Pixel data is shifted in 8 bits at a time, so that each byte contains information for 4 pixels. Therefore, a total of 200 pulses on CL clock signal. After the row has been shifted in, the LE (latch enable) signal is pulsed high to load the data into the output latch. Finally, to write the row, the OE signal should be raised simultaneously with the gate driver CKV signal.
This much was easy enough to guess based on the public information. However, doing just that, nothing happened. One crucial piece of information is still missing: the meaning of the 2 bits that define the state of each pixel:
| Bit 1 | Bit 0 | Action |
|---|---|---|
| 0 | 0 | No action |
| 0 | 1 | Draw black |
| 1 | 0 | Draw white |
| 1 | 1 | No action |
And guess who was using 0x00 0xFF as test pattern..
Conclusion
These waveforms are enough to get basic images onto the E-Ink panel. In reality the subject is a lot more complex: there are all kinds of temperature dependencies and various ways how to switch pixels as quickly and accurately as possible. In fact, when you buy through the official channels instead of eBay, the panel manufacturer will provide a waveform file which contains all of the timings in some proprietary format.