KICAD-導出PCB規則設置

目前版本5.1.5.3，沒有導出選項。

但是工程.pro文件是文本文件，這些設置都在.pro中[pcbnew]下：

[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=0
MinTrackWidth=0.1524
MinViaDiameter=0.6
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.1524
TrackWidth1=0.2032
TrackWidth2=0.1524
TrackWidth3=0.254
TrackWidth4=0.35
TrackWidth5=0.508
TrackWidth6=1
ViaDiameter1=0.7112
ViaDrill1=0.4064
ViaDiameter2=0.6
ViaDrill2=0.3
ViaDiameter3=0.7
ViaDrill3=0.4
ViaDiameter4=0.9
ViaDrill4=0.6
dPairWidth1=0.2032
dPairGap1=0.2
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.051
SolderMaskMinWidth=0.09999999999999999
SolderPasteClearance=0
SolderPasteRatio=-0

覆蓋目標.pro即可修改這些佈線設置。

可以根據“導入設置”中的分類取理解.pro各項數據。