ARM926EJ-S 32-bit RISC CPU with 8KB I-Cache &8KB D-Cache
Frequency up to 200MHz@1.8V core power operation voltage
JTAG interface supported for development and debugging
https://bbs.21ic.com/icview-542928-1-1.html
The ARM subsystem is based on the ARM1176JZF-S core
The memory system has dual external memory ports, DRAM and Flash/ROM.
The DRAM port can be configured to support mobile DDR, DDR, mobile SDRAM and SDRAM.
The Flash/ROM port supports NOR-Flash, NAND-Flash,OneNAND, CF and ROM type external memory.
內部
srom:// 32KB0x0800_0000 0x0BFF_FFFF 64MB Internal ROM
sram:// 8KB0x0C00_0000 0x0FFF_FFFF 64MB Stepping Stone (Boot Loader)0x0000_0000 0x07FF_FFFF 128MB Booting Device Region by XOM Setting Mirrored Region ???
外部
DRAM:
DRAM Controller of the Memory Port1
0x5000_0000 0x5FFF_FFFF 256MB
0x6000_0000 0x6FFF_FFFF 256MB
FLASH:
supports NOR-Flash, NAND-Flash,OneNAND, CF and ROM type external memory.
boot
The operating mode is mainly classified into six categories according to the boot device. The boot device can be among SROM, NOR, OneNAND, MODEM and Internal ROM
// 對於不同的啓動配置(OM[4:0]決定),memory map不同// 沒找到合適的官方boot資料,以下來源於網絡(1) 上電後首先運行iRom（BL0）內的代碼，主要完成時鐘和看門狗等外圍器件的初始化。
(2) 拷貝SD卡或者NnadFlash中的前4k(BL1)代碼到片內ram(墊腳石)去運行，主要工作是配置主存儲器SDRAM。並將剩餘的BL1和BL2加載到SDRAM上。 // 這裏有問題??應該是8KB吧,沒找到資料,ε=(´ο｀*)))唉(3) 完成後將程序的入口跳轉到SDRAM中的BL2繼續運行。並將存儲設備上的OS加載到SDRAM運行。
(4) 將程序的入口跳轉到拷貝到SDRAM上的OS的入口進行運行。
s5pv210
總介
It integrates the ARM Cortex-A8 core, which implements the ARM architecture V7-A with supporting peripherals.
S5PV210 has an interface to external memory that is capable of sustaining heavy memory bandwidths required in
high-end communication services. The memory system has Flash/ ROM external memory ports for parallel access and DRAM port to meet high bandwidths.
DRAM controller supports LPDDR1 (mobile DDR), DDR2, or LPDDR2.
Flash/ ROM port supports NAND Flash, NOR-Flash, OneNAND, SRAM, and ROM type external memory.
內部
IROM:64KB
0xD000_0000 0xD000_FFFF 64KB IROM
IRAM:96KB
0xD002_0000 0xD003_7FFF 96KB IRAM
0x0000_0000 0x1FFF_FFFF 512MB Boot area Mirrored region depending on the boot mode.
外部
DRAM:0x2000_0000 0x3FFF_FFFF 512MB DRAM 00x4000_0000 0x7FFF_FFFF 1024MB DRAM 1
FLASH:
supports NAND Flash, NOR-Flash, OneNAND, SRAM, and ROM type external memory
boot
The boot loader is largely composed of iROM, first and second boot loaders.
The characteristics of these boot loaders are:
• iROM code: Contains small and simple code, which is platform-independent and stored in internal memory
• First boot loader: Contains small and simple code, which is platform-independent and stored in external
memory device. Related to secure booting.
• Second boot loader: Contains complex code, which is platform-specific and stored in external memory device.
The booting device can be chosen from following list:
• General NAND Flash memory
• OneNAND memory
• SD/ MMC memory (such as MoviNAND and iNAND)
• eMMC memory
• eSSD memory
• UART and USB devices
exynos4412
總介
ARM Cortex-A9 based Quad CPU Subsystem with NEON
32/32/32/32 KB I/D Cache,1 MB L2 Cache
Operating frequency up to 1.4 GHz
64 KB ROM for secure booting and 256 KB RAM for security function
The memory system has dedicated DRAM ports and Static Memory port.
RAM: The dedicated DRAM ports support LPDDR2 interface for high bandwidth.
FLASH: Static Memory Port supports NOR Flash and ROM type external memory and components.
boot：
Due to the recent increase in the prices of NOR flash memory and the moderately priced DRAM, and NAND flash,customers prefer to execute boot code on NAND flash and execute the main code on DRAM.
The boot code in Exynos 4412 can be executed on external NAND flash.
It copies NAND flash data to DRAM. To validate the NAND flash data, Exynos 4412 includes hardware Error Correction Code (ECC).
After the NAND flash content is copied to DRAM, main program will be executed on DRAM
The features of NAND flash controller are:
Auto boot: The boot code is transferred to internal SRAM during reset. After the transfer, the boot code will be executed on the SRAM.
OM[5:1] 配置1st device 和 2nd device // If it fails to download BL1 from the first booting device, the iROM code tries to download BL1 from the second booting device (USB or SDMMC_CH2).
General NAND flash memory
SD/MMC memory card
eMMC memory
USB device
The boot loader is comprises the first and the second boot loaders.
The characteristics of these boot loaders are:
iROM: It is a small and simple code to initiate SOC. It is implemented on internal ROM of SOC.
First boot loader (BL1): It is chip-specific and stored in external memory device.
Second boot loader (BL2): It is platform-specific and stored in external memory device.
三星不提供 BL1 BL2
-------------------具體啓動流程
iROM is placed in internal 64 KB ROM. It initializes basic system functions such as clock and stack.
iROM loads BL1 image from a specific booting device to internal 256 KB SRAM. The booting device is
selected by Operating Mode (OM) pins. According to the secure boot key values, iROM may do an integrity
check on BL1 image.
BL1 initializes system clock, and DRAM controller. After initializing DRAM controller, it loads OS image from
the booting device to DRAM. According to the secure boot key values, BL1 can do an integrity check on the
OS image.
After the booting completes, BL1 jumps to the operating system.
RK-3288
總介
Quad-core ARM Cortex-A17 MPCore processor, a high-performance, low-power and cached application processor
內部
Internal on-chip memory
20KB BootRom
100KB internal SRAM for security and non-security access, detailed size is programmable
RK3288 provides system boot from off-chip devices such as SDMMC card,8bits async nand flash or toggle nand flash, SPI nor or nand, and eMMC memory. When boot code is not ready in these devices, also provide system code download into them by USB OTG interface.
啓動過程爲二級啓動(boot loader)
一級啓動:
從bootrom啓動,根據配置加載設備前100KB進sram,並執行sram中的代碼
二級啓動:
用戶代碼:
一般爲初始化ddr,然後拷貝二級啓動設備上的全部代碼進入ddr.然後跳轉到ddr.
