VIVADO無法生成比特流
今天在做verilog實驗的時候，在生成比特流這一步，發生瞭如下報錯
報錯如下：
[DRC NSTD-1] Unspecified I/O Standard: 10 out of 10 logical ports use I/O standard (IOSTANDARD) value ‘DEFAULT’, instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: x[7], x[6], x[5], x[4], x[3], x[2], x[1], and y[2:0].
原來是缺少了一個文件，解決方法：
根據上面的報錯，我們將如下代碼
set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
set_property SEVERITY {Warning} [get_drc_checks RTSTAT-1]
寫到一個txt文件，然後更改爲.tcl格式，保存
再按照這樣。把我們剛剛保存的文件導入，就OK啦