ARM GIC （二）GICv3 中斷安全態、分組及編程模型

The GICv3 architecture supports the ARM TrustZone technology. Each INTID must be assigned a group and security setting.

每一箇中斷都需要配置安全態和分組。

中斷安全態及中斷分組

gicv3 爲了兼容 armv8 引入了支持2種安全狀態（secure state），根據 secure 狀態，分爲安全中斷和非安全中斷。也可以配置成只支持一種安全狀態。顯而易見，下圖中前兩組是安全中斷，NSG1 是非安全中斷。

In a system with two Security states, an interrupt is configured as one of the following:
A Group 0：ARM expects these interrupts to be handled at EL3.
A Secure Group 1：ARM expects these interrupts to be handled at Secure EL1.
A Non-secure Group 1：ARM expects these interrupts to be handled at Non-secure EL2 in systems using virtualization,
                      or at Non-secure EL1 in systems not using virtualization.
 
GICD_IGROUPR<n> and GICD_IGRPMODR<n> configure the interrupt group for SPIs. n is greater than zero.
GICR_IGROUPR0 and GICR_IGRPMODR0 configure the interrupt group for SGIs and PPIs.

中斷安全態控制

中斷安全態由 GICD_CTLR 寄存器的 DS bit，表示是否支持2種安全模式。該位爲0表示支持2種安全態，爲1表示只支持一種安全態，此時只有兩個中斷分組，分別是 group0 & 1，需要注意的是 DS 位被 置1 後只有處理器復位才能清除該標誌。開啓兩個安全態時會在中斷 configure, ack, priority drop, deactivation 中進行安全態檢查。

When GICD_CTLR.DS == 0, LPIs are always Non-secure Group 1 interrupts.
When GICD_CTLR.DS == 1, LPIs are always Group 1 interrupts.

When GICD_CTLR.DS == 0
• The GIC supports two Security states, Secure state and Non-secure state.
• The GIC supports three interrupt groups:
— Group 0.
— Secure Group 1.
— Non-secure Group 1.
這個時候 Group 0 中斷始終是安全態的，非安全態下無法訪問 Group 0 相關的寄存器。

When GICD_CTLR.DS == 1:
• The GIC supports only a single Security state. This can be either Secure state or Non-secure state.
• The GIC supports two interrupt groups:
— Group 0.
— Group 1.

不同安全態下訪問該寄存器的視圖是不一樣的：
當系統支持多箇中斷安全態時從 安全態 訪問該寄存器：

當系統支持多箇中斷安全態時從 非安全態 訪問該寄存器：

當系統支持1箇中斷安全態時從 安全或者非安全態 訪問該寄存器：

中斷線映射 IRQ FIQ

gicv3 將 cpu interface 從gic中抽離，放入到了cpu中，cpu interface 通過 gic stream 接口與gic IRI 進行通信。當gic要發送中斷時gic 通過 gic stream 接口給 cpu interface 發送中斷命令，cpu interface 收到中斷命令後，根據中斷線映射配置，決定是通過 IRQ 還是 FIQ 管腳向 cpu 發送中斷。中斷線映射根據中斷 group 以及當前 cpu 所處的 el 以及 seucre 狀態來決定。

Group 0 interrupts are always signaled as FIQs. Group 1 interrupts are signaled as either IRQs or FIQs depending on the current Security state and Exception level of the PE.

可以看到 group0 的中斷均爲 fiq， el3 時觸發的中斷均爲 fiq，另外可以發現 cpu 在某個安全態下運行，發生了非本安全態的中斷都是 fiq。這是因爲通常我們會把 fiq 路由到 el3 去處理，此時 el3 的組件會完成兩個安全態上下文的切換，把中斷分發給相應的安全或非安全 OS 處理。fiq 路由到 el3，可由 SCR_EL3.FIQ==1 完成。

GICv3 編程模型

Interrupt Controller 中的 Distributor, Redistributor, CPU Interface 需要按照不同順序配置。Distributor 是所有CPU都對應的，這個只要在第一個CPU啓動時配置就可以了，對於 Redistributor 和 CPU Interface 是 PER-CPU 對應的，所以在SECONDARY CPU 啓動時候需要配置各自的組件。

GICv3 regs

Distributor, Redistributor, CPU interface

GICD_* 所有 PE 共享一套
GICR_* 每個 PE 各有一套

CPU interface 每個 PE 各有一套
在 enable system regsiter interface 情況下是
    ICC_*_ELn 
在 memory mapped 情況下是
    GICC_*

部分寄存器是內存映射的 (memory-mapped)，有些是直接系統寄存器訪問 (system register access)。

部分寄存器在支持 legacy 操作時採用內存映射，在 GICv3 模式下使用系統寄存器訪問。

CPU interface 支持採用系統寄存器訪問的方式。

In GICv3 the CPU Interface registers are accessed as System registers (ICC_*_ELn). Software must enable the System register interface before using these registers. This is controlled by the SRE bit in the ICC_SRE_ELn registers, where “n” specifies the Exception level (EL1-EL3).

GICv3 configuration

Global settings

使能親和性路由和各個 group 中斷。GICD_CTLR

• Enable Affinity routing (ARE bits)
• Enables group interrupt

Individual PE settings

redistributor 設置

喚醒即可。GICR_WAKER

• Clear GICR_WAKER .ProcessorSleep to 0
• Poll GICR_WAKER .ChildrenAsleep until it reads 0

cpu interface 配置

使能系統寄存器訪問，設置中斷屏蔽優先級，搶佔配置，設置中斷 EOI 模式，使能對應的中斷。

• Enable System register access ICC_SRE_ELn
• Set priority mask and binary point registers ICC_PMR_EL1 and ICC_BPRn_EL1
  The Priority Mask sets the minimum priority an interrupt must have in order to be forwarded to the PE. The Binary Point register is used for priority grouping and preemption.
• Set EOI mode ICC_CTLR_EL1 and ICC_CTLR_EL3
• Enable signaling of each interrupt group
  The signalling of each interrupt group must be enabled before interrupts of that group will be forwarded by the CPU interface to the PE. To enable signaling software must write to ICC_IGRPEN1_EL1 register for Group 1 interrupts and ICC_IGRPEN0_EL1 registers for Group 0 interrupts. ICC_IGRPEN1_EL1 is banked by Security state. This means that ICC_GRPEN1_EL1 controls Group 1 for the current Security state. At EL3, software can access both Secure Group 1 interrupt enables and Non-secure Group 1 interrupt enables using ICC_IGRPEN1_EL3.

處理器設置

爲了讓處理器能夠處理中斷，處理器自身也要做相應的配置。

• Routing controls。SCR_EL3 and HCR_EL2，分別可以配置中斷到 EL3 還是 EL2 處理。
  路由選擇決定了中斷被哪個 el 所處理，即採用哪個異常級的中斷向量表。
• Interrupt masks。除了 GIC 會進行中斷屏蔽外，處理器本身 PSTATE 的 DAIF 也可以進行屏蔽。
• Vector table。VBAR_ELn

以上三者除了 PSTATE 復位會有值外其他寄存器都是 UNKNOWN，因此必須初始化。

SPI PPI SGI configuration

前面把基本的環境都配置好了，對於每個中斷而言，還有各自的屬性需要配置。
SPI 使用 GICD_*，PPI 和 SGI 使用 GICR_*。這裏屬性就是中斷優先級、中斷分組、觸發類型、使能，對於 SPI 還有目標PE。

1. Priority (GICD_IPRIORITYn, GICR_IPRIORITYn)
0x00 is the highest possible priority, and 0xFF is the lowest possible priority. 
An interrupt controller is not required to implement all 8 priority bits. A minimum of 5
bits must be implemented if the GIC supports two Security states. A minimum of 4 bits
must be implemented if the GIC support only a single Security state.

2. Group (GICD_IGROUPn, GICD_IGRPMODn, GICR_IGROUP0, GICR_IGRPMOD0)
前面提到了，每個中斷都必須分配到中斷組裏去，它們可以分別是 Group 0, Secure Group 1 and Non-secure Group 1.

3. Edge-triggered/level-sensitive (GICD_ICFGRn, GICR_ICFGRn)
SGIs are always treated as edge-triggered, and therefore GICR_ICFGR0 behaves as RAO/WI for these interrupts.

4. Enable (GICD_ISENABLERn, GICD_ICENABLER, GICR_ISENABLER0, GICR_ICENABLER0)
Each INTID has an enable bit. Set-enable registers and Clear-enable registers remove the requirement to perform read-modify-write routines.
推薦某個中斷在上面配置完成前都不要使能該中斷。特別的，如果要變更某中斷的配置，推薦首先不使能這個中斷然後再繼續操作。

5. 對於 SPI 而言，還需要配置其目標 PE。GICD_IROUTERn
GICD_IROUTERn.Interrupt_Routing_Mode == 0
The SPI is to be delivered to the PE A.B.C.D, the affinity co-ordinates specified in the register.

GICD_IROUTERn.Interrupt_Routing_Mode == 1
The SPI can be delivered to any connected PE that is participating in distribution of the interrupt group. 
意思是每次中斷觸發去往哪個核不是由軟件決定的。
This type of routing is referred to as 1-of-N.

A PE can opt-out of receiving 1-of-N interrupts. This is controlled by the DPG1S, DPG1NS and DPG0 bits in GICR_CTLR.

後記

從上面的配置過程看，關閉或者不響應某個中斷可以從各個層面去控制。
在 distributor 處可以關閉某個 group 的中斷，注意這裏是全局關某個 group，GICD_CTLR。
在 cpu interface 處也可以關閉該 interface 某個 group 的中斷，ICC_IGRPEN0_EL1 & ICC_IGRPEN1_EL1 or ICC_IGRPEN1_EL3。
對於每個中斷，同樣有單獨的使能寄存器。(GICD_ISENABLERn, GICD_ICENABLER, GICR_ISENABLER0, GICR_ICENABLER0)。
當然 PE 層面也可以實現屏蔽，這是全局屏蔽。DAIF。