參考資料
參考：《Cortex-M0+ Devices Generic User Guide》
http://www.keil.com/dd/docs/datashts/arm/cortex_m0p/r0p0/dui0662a_cortex_m0p_r0p0_dgug.pdf
http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/DUI0497A_cortex_m0_r0p0_generic_ug.pdf
表4.2.6
要注意的幾點：
（1）Cortex-M0中NVIC-IPR共有8個寄存器，而每個寄存器管理4個IRQ中斷，所以M0+的IRQ中斷源最多隻支持32個了，再加上16個內核中斷，也就是說M0+最多就是48箇中斷源；
（2）優先級寄存器裏面的配置值越低表明相應的中斷優先級越高；
（3）每個PRIxx的8位中只有最高兩位[7:6]有效，也就是說實際上M0+的優先級只有四個即0，1，2，3，其中0的優先級是最高的；
（4）這是比較容易忽略的問題，即word-accessible，也就是說這幾個寄存器都只能按字操作，切記不要使用指向字節的指針只對某個單獨中斷的優先級進行配置。
（5）M0的嵌套相對比較簡單，即只要相應中斷的優先級比較高即可隨時搶佔比它優先級低的中斷服務。
（6）內核中斷，其中斷優先級則由SCB模塊的SCB_SHPR寄存器來管理，可參考手冊4.3.7 System Handler Priority Registers，實際上我們平時常用的就是systemtick中斷，其優先級配置同NVIC。
另外，如果我們不對優先級進行配置的話，則默認相應中斷源的向量號越低其優先級越高。
NVIC_SetPriority解讀
我們看一下一些相關定義：
stm32f0xx.h
/**
* @brief STM32F0xx Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
#define __CM0_REV 0 /*!< Core Revision r0p0 */
#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/*!< Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
/****** STM32F-0 specific Interrupt Numbers *********************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt*/
FLASH_IRQn = 3, /*!< FLASH Interrupt*/
RCC_IRQn = 4, /*!< RCC Interrupt*/
EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
TS_IRQn = 8, /*!< TS Interrupt*/
DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts*/
ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts*/
TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 15, /*!< TIM2 Interrupt */
TIM3_IRQn = 16, /*!< TIM3 Interrupt */
TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts*/
TIM14_IRQn = 19, /*!< TIM14 Interrupt */
TIM15_IRQn = 20, /*!< TIM15 Interrupt */
TIM16_IRQn = 21, /*!< TIM16 Interrupt */
TIM17_IRQn = 22, /*!< TIM17 Interrupt */
I2C1_IRQn = 23, /*!< I2C1 Interrupt */
I2C2_IRQn = 24, /*!< I2C2 Interrupt*/
SPI1_IRQn = 25, /*!< SPI1 Interrupt*/
SPI2_IRQn = 26, /*!< SPI2 Interrupt */
USART1_IRQn = 27, /*!< USART1 Interrupt*/
USART2_IRQn = 28, /*!< USART2 Interrupt */
CEC_IRQn = 30 /*!< CEC Interrupt */
} IRQn_Type;
static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
else {
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
}
core_cm0.h
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register*/
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register*/
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register*/
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
計算方法舉例，如：
NVIC_SetPriority(SPI1_IRQn, 0x25);
實際計算的是
NVIC->IP[6] = (NVIC->IP[6] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
計算中用到的一些結果（自己手動算一次就明白了）：
SPI1_IRQn = 25 = 0b11001
_IP_IDX(IRQn) = 6
_BIT_SHIFT(IRQn) = (0x25&0x03)*8 = 8
~(0xFF << _BIT_SHIFT(IRQn) = ~0x0000FF00= 0xFFFF00FF
因此，(NVIC->IP[6] & ~(0xFF << _BIT_SHIFT(IRQn)))就是清零的意思，後面
(priority << (8 - __NVIC_PRIO_BITS) = 25<<6 = 0b11001000000=0x640
(priority << (8 - __NVIC_PRIO_BITS) &0xFf = 0x040
所以下面這句就是priority選最低兩位， 然後左移到相應的4個IPR寄存器中的一個。比如SPI1_IRQn在第2個，
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)) = 0x04000
因此，NVIC->IP[6]中第25箇中斷的優先級是0x25的有效最低兩位，即0x01
所以，下面兩個設置是完全等價的
NVIC_SetPriority(SPI1_IRQn, 0x25);
NVIC_SetPriority(SPI1_IRQn, 0x01);