夏宇聞verilog第十章答案_練習三

源碼：

module wavegene(
			clk_in_10M,
			clk_out,
			reset
			);
input clk_in_10M,reset;
output clk_out;

reg clk_out2;
reg [8:0] cnt;//需要計數300次即可，512即可
assign clk_out = clk_out2;

always @(posedge clk_in_10M or posedge reset)
begin
	if(reset == 1) 
		clk_out2 = 1'b0;
	else 
		if(cnt < 9'd300)
			begin
				if(cnt < 9'd100)
					clk_out2 <= 1'b1;
				else
					clk_out2 <= 1'b0;
					
				cnt <= cnt + 1;
			end
		else 
			cnt <= 9'd0;	
end 

endmodule

測試代碼：

`timescale 1ns/1ns
`define Cycle 100
module wavegenetb;
reg clk_in_10M,reset;
wire clk_out;

initial
begin
	clk_in_10M	= 1'h0;
	reset	= 1'h1;
	#20
	reset	= 1'h0;
end

always #(`Cycle/2) clk_in_10M = ~clk_in_10M;

wavegene mywavegene(
			.clk_in_10M(clk_in_10M),
			.clk_out(clk_out),
			.reset(reset)
			);
endmodule

仿真結果：