1、在前面《有限状态机--更正版》的建模模块中，我采取了左图方法建模，得出下图一正确结果
module fsm5(clock,reset,coin,news_out);
input clock,reset;input [1:0]coin;
output news_out;
reg [1:0]pres_state;
reg rnews_out;
parameter s0=2'd0;
parameter s1=2'd1;
parameter s2=2'd2;
parameter s3=2'd3;
always @(posedge clock)
begin
if(!reset)
pres_state<=s0;
else
case(pres_state)
s0 :
case(coin)
2'd0 :
begin
pres_state<=s0;
rnews_out<=0;
end
2'd1 :
begin
pres_state<=s1;
rnews_out<=0;
end
2'd2 :
begin
pres_state<=s2;
rnews_out<=0;
end
endcase
s1 :
case(coin)
2'd0 :
begin
pres_state<=s1;
rnews_out<=0;
end
2'd1 :
begin
pres_state<=s2;
rnews_out<=0;
end
2'd2 :
begin
pres_state<=s0;
rnews_out<=1;
end
endcase
s2 :
case(coin)
2'd0 :
begin
pres_state<=s2;
rnews_out<=0;
end
2'd1 :
begin
pres_state<=s0;
rnews_out<=1;
end
2'd2 :
begin
pres_state<=s0;
rnews_out=1;
end
endcase
s3 :
begin
rnews_out=1;
pres_state<=s0;
end
endcase
end
图一
2、但我若添加一个next_state中间寄存器，编写代码。出现下面图2结果：
module finite_state_module(clock,reset,coin,news_out);
input clock,reset;
input [1:0]coin;
output news_out;
reg [1:0]pres_state,next_state;
reg rnews_out;
parameter s0=2'd0;
parameter s1=2'd1;
parameter s2=2'd2;
parameter s3=2'd3;
always @(posedge clock,negedge reset)
begin
if(!reset)
begin
pres_state<=s0;
end
else
pres_state<=next_state;
end
//这种建模方式与方法一的差别即是方法二采用两个过程块，并设置了中间变量next_state，第一个always过程块是根据时钟变化，将 pres_state置为next_state，而第二个always过程块是根据 pres_state,coin的变化，更改next_state和news_out。而方法一种采用一个always过程块，当上升沿到来时，根据coin的变化，直接更改pres_state和news_out的状态。
always @(pres_state,coin)
begin
case(pres_state)
s0 :
case(coin)
2'd0 :
begin
next_state=s0;
rnews_out=0;
end
2'd1 :
begin
next_state=s1;
rnews_out=0;
end
2'd2 :
begin
next_state=s2;
rnews_out=0;
end
endcase
s1 :
case(coin)
2'd0 :
begin
next_state=s1;
rnews_out=0;
end
2'd1 :
begin
next_state=s2;
rnews_out=0;
end
2'd2 :
begin
next_state=s0;
rnews_out=1;
end
endcase
s2 :
case(coin)
2'd0 :
begin
next_state=s2;
rnews_out=0;
end
2'd1 :
begin
next_state=s0;
rnews_out=1;
end
2'd2 :
begin
next_state=s0;
rnews_out=1;
end
endcase
s3 :
begin
rnews_out=1;
next_state=s0;
end
endcase
end
assign news_out=rnews_out;
endmodule
图二
图一图一对比可知，图二在仿真时刻30ns，news_out就变成了“1”，但此时暂时只输入了两个“01”，即投入两个5毛，还没达到一块五状态。除此之外，后面的仿真波形都是对的。