Placement Optimization with Deep Reinforcement Learning
author use deep reinforcement learning to complish the placement stage of physical design. and the deep reinforcement learning is based on graph (I can't understand this, why one logic structure can be replaced by ratio?).
input graph: v1, v2,......,vn
placement location: l1,l2,......,ln
reward function: R
we should get a result that has lagest R.
there are three example: placement optimization overview:
the reward function varies for different problems. For example, for TensorFlow graph placement, we use negative runtime of a training step of the placed deep network model. For ASIC and FPGA netlists, the reward is more complex and should include various metrics related to power and timing (e.g. total wirelength, routability congestion, and cell density).