It is not necessary to spell out（寫出） the recipes for compiling the individual C source files, because make can figure them out（推導出）: it has an implicit（隱式的） rule for updating a ‘.o’ file from a correspondingly named ‘.c’ file using a ‘cc -c’ command. For example, it will use the recipe ‘cc -c main.c -o main.o’ to compile main.c into main.o. We can therefore omit（忽略） the recipes from the rules for the object files.（這段話的意思是說，在編寫目標文件的規則時可以省略命令）
When a ‘.c’ file is used automatically in this way, it is also automatically added to the list of prerequisites. We can therefore omit the ‘.c’ files from the prerequisites, provided we omit the recipe. （在編寫目標文件的規則時，依賴條件中可以忽略對應的.c文件）
Here is the entire example, with both of these changes, and a variable objects as suggested above:
objects = main.o kbd.o command.o display.o \
insert.o search.o files.o utils.o
edit : $(objects)
cc -o edit $(objects)
main.o : defs.h
kbd.o : defs.h command.h
command.o : defs.h command.h
display.o : defs.h buffer.h
insert.o : defs.h buffer.h
search.o : defs.h buffer.h
files.o : defs.h buffer.h command.h
utils.o : defs.h
.PHONY : clean
clean :
rm edit $(objects)
This is how we would write the makefile in actual practice.
Because implicit rules are so convenient（方便的）, they are important. You will see them used frequently.