轉自：
一、Latency 基礎：
AXI latency 是比較關鍵的部分，可以採用VIP的latency機制模擬硬件的latency 信息；其中latency機制的使用按照作用主體分爲兩塊：一個是針對master VIP的，一個是針對Slave VIP的；
根據axi的握手機制：
寫通道操作： master 負責操作：awvalid 、awaddr、wvalid 、 wdata 、 wlast 而slave 負責操作：awready 、wready
讀通道操作：master 負責操作：arvalid、 araddr、ready 而slave 負責操作：arready、rdata 、rlast和rvalid
寫響應通道： slave 負責發送 bvalid ， master 負責操作bready，一旦master 拉高bready，那麼bresp會立刻發送到master部分作爲響應。
1）master vip + slave DUT；
vip作爲master的情況下，主要操作包括axi 寫、axi 讀、axi 寫響應；
wvalid_delay：由master 主動控制，
rready_delay:由master 主動控制；
2）master DUT + slave VIP：
vip作爲slave 的情況，
wready_delay：由slave 來進行控制，什麼時候給出ready信號，一遍master可以寫入slave；
rvalid_delay：讀數據時，由slave 來進行控制什麼時候給數據。
二、AXI latency 宏以及reference event
AXI delay control attributes
Description of address_valid_delay for reference
event PREV_ADDR_VALID for write address channel
Addr_valid_delay defines the number of cycles the AWVALID signal is delayed with respect to the reference event PREV_ADDR_VALID. It is applicable only for the ACTIVE MASTER.
Description of address_valid_delay for
reference event PREV_ADDR_HANDSHAKE for write address channel
Addr_valid_delay defines the number of cycles the AWVALID signal is delayed with respect to the reference event PREV_ADDR_HANSHAKE. It is applicable only for the ACTIVE MASTER.
Description of address_valid_delay for
reference event PREV_ADDR_VALID for read address channel
Addr_valid_delay defines the number of cycles the ARVALID signal is delayed with respect to the reference event PREV_ADDR_VALID. It is applicable only for the ACTIVE MASTER.
Description of address_valid_delay for
reference event PREV_ADDR_HANDSHAKE for read address channel
Addr_valid_delay defines the number of cycles the ARVALID signal is delayed with respect to the reference event PREV_ADDR_HANDSHAKE. It is applicable only for the ACTIVE MASTER.
Description of bvalid_delay for reference
event LAST_DATA_HANDSHAKE for write response channel
Represents delay in terms of clock cycle for bvalid assertion with respect to the reference event LAST_DATA_HANDHAKE. It is applicable only for the ACTIVE SLAVE.
Description of bvalid_delay for
reference event ADDR_HANDSHAKE for write response channel
Represents delay in terms of clock cycles for bvalid assertion with respect to the reference event ADDR_HANDHAKE. It is applicable only for the ACTIVE SLAVE.
Description of first rvalid_delay for
reference event READ_ADDR_VALID for read data channel
Represents a delay for the first RVALID assertion with respect to the reference event READ_ADDR_VALID. It is applicable only for the ACTIVE SLAVE.
Description of first rvalid_delay for
reference event READ_ADDR_HANDSHAKE for read data channel
Represents a delay for the first RVALID assertion with respect to the reference event READ_ADDR_HANDSHAKE.
Description of first wvalid_delay for
reference event WRITE_ADDR_VALID for write data channel
Represents a delay for the first WVALID assertion with respect to the reference event WRITE_ADDR_VALID.
Description of first wvalid_delay for
reference event WRITE_ADDR_HANDSHAKE for write data channel
Represents a delay for the first WVALID assertion with respect to the reference event WRITE_ADDR_HANDSHAKE.
Description of first wvalid_delay for reference event PREV_WRITE_DATA_HANDSHAKE for write data channel
Represents a delay for the first WVALID assertion with respect to the reference event PREV_WRITE_DATA_HANDSHAKE.
Description of rready_delay for
reference event RVALID for read data channel
Represents a delay for the first RREADY assertion with respect to the reference event RVALID.
Description of wready_delay for reference event WVALID for write data channel
Represents a delay for the first WREADY assertion with respect to the reference event WVALID.
Description of bready_delay for reference event BVALID for write response channel
If configuration parameter svt_axi_port_configuration :: default_bready is FALSE, this member defines the BREADY signal delay in number of clock cycles. The reference event for this delay is assertion of bvalid.
If the configuration parameter svt_axi_port_configuration :: default_bready is TRUE, this member defines the number of clock cycles for which BREADY signal should be deasserted after each handshake, before pulling it up again to its default value.
Represents the bready delay for reference event BVALID for default_bready is TRUE. It is applicable only for the ACTIVE MASTER.
Description of next rvalid_delay for reference event PREV_RVALID for read data channel
Represents a delay for the next RVALID assertion with respect to the reference event PREV_RVALID.
Description of next rvalid_delay for reference event PREV_READ_HANDSHAKE
for read data channel
Represents a delay for the next RVALID assertion with respect to the reference event PREV_READ_HANDSHAKE.
Description of next wvalid_delay for reference event PREV_WVALID for
write data channel
Represents a delay for the next WVALID assertion with respect to the reference event PREV_WVALID.
Description of next wvalid_delay for reference
event PREV_WRITE_HANDSHAKE for write data channel
Represents a delay for the next WVALID assertion with respect to the reference event PREV_WRITE_HANDSHAKE.
Description of addr_ready delay for reference
event ADDR_VALID for write address channel
If the configuration parameter svt_axi_port_configuration :: default_awready is FALSE, this member defines the AWREADY signal delay in number of clock cycles. The reference event used for this delay is addr_valid.
If the configuration parameter svt_axi_port_configuration :: default_awready is TRUE, this member defines the number of clock cycles for which AWREADY signal should be deasserted after each handshake, before pulling it up again to its default value. It is applicable only for the ACTIVE SLAVE.
Description of addr_valid_delay for reference event FIRST_DATA_HANDSHAKE_DATA_BEFORE_ADDR for read address channel
Addr_valid_delay defines the number of cycles the ARVALID signal is delayed with respect to the reference event FIRST_DATA_HANDSHAKE_DATA_BEFORE_ADDR. It is applicable only for the ACTIVE MASTER.
Description of addr_ready_delay for reference
event ADDR_VALID for read address channel
If the configuration parameter svt_axi_port_configuration :: default_arready is FALSE, this member defines the ARREADY signal delay in number of clock cycles. The reference event used for this delay is addr_valid.
If the configuration parameter svt_axi_port_configuration :: default_arready is TRUE, this member defines the number of clock cycles for which ARREADY signal should be deasserted after each handshake, before pulling it up again to its default value. It is applicable only for the ACTIVE SLAVE.
Description of addr_valid_delay for reference event FIRST_WVALID_DATA_BEFORE_ADDR
for write address channel
Addr_valid_delay defines the number of cycles the AWVALID signal is delayed with respect to the reference event FIRST_WVALID_DATA_BEFORE_ADDR. It is applicable only for the ACTIVE MASTER.
Description of addr_valid_delay for reference event FIRST_DATA_HANDSHAKE_DATA_BEFORE_ADDR
for write address channel
Addr_valid_delay defines the number of cycles the AWVALID signal is delayed with respect to the reference event FIRST_DATA_HANDSHAKE_DATA_BEFORE_ADDR. It is applicable only for the ACTIVE MASTER.
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原文鏈接：https://blog.csdn.net/wuhenge120/article/details/114824255