原创 Verilog variable select group of bits from a vector
Verilog-2001 adds the capability to use variables to select a group of bits from a vector. ◆ The starting point of the
2018-08-27 17:53:17
5
原创 Difference between physically exclusive，logically exclusive and async clock groups
physically_exclusive:Means Timing paths between these clock domains are false, but only one clock can exist in the desi
2018-08-27 17:53:15
188