ARM v8指令集（手冊）

1、Conditional Branch

 - B.cond label

Branch: conditionally jumps to program-relative label 
if cond is true.

 - CBNZ Wn, label

Compare and Branch Not Zero: conditionally jumps to
 program-relative label if Wn is not equal to zero.

 - CBNZ Xn, label

Compare and Branch Not Zero (extended): conditionally
 jumps to label if Xn is not equal to zero.

 - CBZ Wn, label

Compare and Branch Zero: conditionally jumps to label if
 Wn is equal to zero.

 - CBZ Xn, label

Compare and Branch Zero (extended): conditionally jumps to 
label if Xn is equal to zero.

 - TBNZ Xn|Wn, #uimm6, label

Test and Branch Not Zero: conditionally jumps to label if 
bit number uimm6 in register Xn is not zero.
The bit number implies the width of the register, which 
may be written and should be disassembled as Wn
if uimm is less than 32. Limited to a branch offset 
range of ±32KiB.

 - TBZ Xn|Wn, #uimm6, label

Test and Branch Zero: conditionally jumps to label if bit
 number uimm6 in register Xn is zero. The bit
number implies the width of the register, which may be
 written and should be disassembled as Wn if
uimm6 is less than 32. Limited to a branch offset range 
of ±32KiB.

2、Unconditional Branch (immediate)

Unconditional branches support an immediate branch offset range of ±128MiB.

B label
Branch: unconditionally jumps to pc-relative label.
BL label
Branch and Link: unconditionally jumps to pc-relative
 label, writing the address of the next sequential
instruction to register X30.

3、Unconditional Branch (register)

 - BLR Xm

Branch and Link Register: unconditionally jumps to address
 in Xm, writing the address of the next
sequential instruction to register X30.

 - BR Xm

Branch Register: jumps to address in Xm, with a hint to 
the CPU that this is not a subroutine return.

 - RET {Xm}

Return: jumps to register Xm, with a hint to the CPU that 
this is a subroutine return. An assembler shall
default to register X30 if Xm is omitted.

4、Load-Store Single Register

 - LDR Wt, addr

Load Register: loads a word from memory addressed by addr
 to Wt.

 - LDR Xt, addr

Load Register (extended): loads a doubleword from memory 
addressed by addr to Xt.

 - LDRB Wt, addr

Load Byte: loads a byte from memory addressed by addr, 
then zero-extends it to Wt.

 - LDRSB Wt, addr

Load Signed Byte: loads a byte from memory addressed by 
addr, then sign-extends it into Wt.

 - LDRSB Xt, addr

Load Signed Byte (extended): loads a byte from memory 
addressed by addr, then sign-extends it into Xt.

 - LDRH Wt, addr

Load Halfword: loads a halfword from memory addressed by 
addr, then zero-extends it into Wt.

 - LDRSH Wt, addr

Load Signed Halfword: loads a halfword from memory 
addressed by addr, then sign-extends it into Wt.

 - LDRSH Xt, addr

Load Signed Halfword (extended): loads a halfword from 
memory addressed by addr, then sign-extends
it into Xt.

 - LDRSW Xt, addr

Load Signed Word (extended): loads a word from memory 
addressed by addr, then sign-extends it into
Xt.

 - STR Wt, addr

Store Register: stores word from Wt to memory addressed by 
addr.

 - STR Xt, addr

Store Register (extended): stores doubleword from Xt to
 memory addressed by addr.

 - STRB Wt, addr

Store Byte: stores byte from Wt to memory addressed by
 addr.

 - STRH Wt, addr

Store Halfword: stores halfword from Wt to memory 
addressed by addr.

5、Load-Store Single Register (unscaled offset)

 - LDUR Wt, [base,#simm9]

Load (Unscaled) Register: loads a word from memory 
addressed by base+simm9 to Wt.

 - LDUR Xt, [base,#simm9]

Load (Unscaled) Register (extended): loads a doubleword
 from memory addressed by base+simm9 to Xt.

 - LDURB Wt, [base,#simm9]

Load (Unscaled) Byte: loads a byte from memory addressed 
by base+simm9, then zero-extends it into Wt.

 - LDURSB Wt, [base,#simm9]

Load (Unscaled) Signed Byte: loads a byte from memory 
addressed by base+simm9, then sign-extends it into Wt.

 - LDURSB Xt, [base,#simm9]

Load (Unscaled) Signed Byte (extended): loads a byte from 
memory addressed by base+simm9, then sign-extends it into Xt.

 - LDURH Wt, [base,#simm9]

Load (Unscaled) Halfword: loads a halfword from memory 
addressed by base+simm9, then zero-extends it into Wt.

 - LDURSH Wt, [base,#simm9]

Load (Unscaled) Signed Halfword: loads a halfword from 
memory addressed by base+simm9, then signextends it into Wt.

 - LDURSH Xt, [base,#simm9]

Load (Unscaled) Signed Halfword (extended): loads a 
halfword from memory addressed by base+simm9,
then sign-extends it into Xt.

 - LDURSW Xt, [base,#simm9]

Load (Unscaled) Signed Word (extended): loads a word from 
memory addressed by base+simm9, then sign-extends it into Xt.

 - STUR Wt, [base,#simm9]

Store (Unscaled) Register: stores word from Wt to memory addressed by base+simm9.

 - STUR Xt, [base,#simm9]

Store (Unscaled) Register (extended): stores doubleword 
from Xt to memory addressed by base+simm9.

 - STURB Wt, [base,#simm9]

Store (Unscaled) Byte: stores byte from Wt to memory 
addressed by base+simm9.

 - STURH Wt, [base,#simm9]

Store (Unscaled) Halfword: stores halfword from Wt to 
memory addressed by base+simm9.

6、Load Single Register (pc-relative, literal load)

 - LDR Wt, label | =value

Load Literal Register (32-bit): loads a word from memory
 addressed by label to Wt.
LDR Xt, label | =value
Load Literal Register (64-bit): loads a doubleword from 
memory addressed by label to Xt.

 - LDRSW Xt, label | =value

Load Literal Signed Word (extended): loads a word from 
memory addressed by label, then sign-extends it into Xt.

7、Load-Store Pair

 - LDP Wt1, Wt2, addr

Load Pair Registers: loads two words from memory addressed 
by addr to Wt1 and Wt2.

 - LDP Xt1, Xt2, addr

Load Pair Registers (extended): loads two doublewords from 
memory addressed by addr to Xt1 and Xt2.

 - LDPSW Xt1, Xt2, addr

Load Pair Signed Words (extended) loads two words from
 memory addressed by addr, then sign-extends them into Xt1 
and Xt2.

 - STP Wt1, Wt2, addr

Store Pair Registers: stores two words from Wt1 and Wt2 to 
memory addressed by addr.

 - STP Xt1, Xt2, addr

Store Pair Registers (extended): stores two doublewords 
from Xt1 and Xt2 to memory addressed by addr.

8、Load-Store Non-temporal Pair

 - LDNP Wt1, Wt2, [base,#imm]

Load Non-temporal Pair: loads two words from memory
 addressed by base+imm to Wt1 and Wt2, with a non-temporal hint.

 - LDNP Xt1, Xt2, [base,#imm]

Load Non-temporal Pair (extended): loads two doublewords 
from memory addressed by base+imm to
Xt1 and Xt2, with a non-temporal hint.

 - STNP Wt1, Wt2, [base,#imm]

Store Non-temporal Pair: stores two words from Wt1 and Wt2 
to memory addressed by base+imm, with a non-temporal hint.

 - STNP Xt1, Xt2, [base,#imm]

Store Non-temporal Pair (extended): stores two doublewords 
from Xt1 and Xt2 to memory addressed by
base+imm, with a non-temporal hint.

9、Load-Store Unprivileged

 - LDTR Wt, [base,#simm9]

Load Unprivileged Register: loads word from memory 
addressed by base+simm9 to Wt, using EL0
privileges when at EL1.

 - LDTR Xt, [base,#simm9]

Load Unprivileged Register (extended): loads doubleword
 from memory addressed by base+simm9 to
Xt, using EL0 privileges when at EL1.

 - LDTRB Wt, [base,#simm9]

Load Unprivileged Byte: loads a byte from memory addressed
 by base+simm9, then zero-extends it into
Wt, using EL0 privileges when at EL1.

 - LDTRSB Wt, [base,#simm9]

Load Unprivileged Signed Byte: loads a byte from memory
 addressed by base+simm9, then sign-extends
it into Wt, using EL0 privileges when at EL1.

 - LDTRSB Xt, [base,#simm9]

Load Unprivileged Signed Byte (extended): loads a byte 
from memory addressed by base+simm9, then
sign-extends it into Xt, using EL0 privileges when at EL1.

 - LDTRH Wt, [base,#simm9]

Load Unprivileged Halfword: loads a halfword from memory
 addressed by base+simm9, then zeroextends it into Wt, using EL0 privileges when at EL1.

 - LDTRSH Wt, [base,#simm9]

Load Unprivileged Signed Halfword: loads a halfword from
 memory addressed by base+simm9, then sign-extends it into Wt, 
 using EL0 privileges when at EL1.

 - LDTRSH Xt, [base,#simm9]

Load Unprivileged Signed Halfword (extended): loads a 
halfword from memory addressed by
base+simm9, then sign-extends it into Xt, using EL0
 privileges when at EL1.

 - LDTRSW Xt, [base,#simm9]

Load Unprivileged Signed Word (extended): loads a word 
from memory addressed by base+simm9, then
sign-extends it into Xt, using EL0 privileges when at EL1.

 - STTR Wt, [base,#simm9]

Store Unprivileged Register: stores a word from Wt to
 memory addressed by base+simm9, using EL0
privileges when at EL1.

 - STTR Xt, [base,#simm9]

Store Unprivileged Register (extended): stores a 
doubleword from Xt to memory addressed by
base+simm9, using EL0 privileges when at EL1.

 - STTRB Wt, [base,#simm9]

Store Unprivileged Byte: stores a byte from Wt to memory
 addressed by base+simm9, using EL0
privileges when at EL1.

 - STTRH Wt, [base,#simm9]

Store Unprivileged Halfword: stores a halfword from Wt to
 memory addressed by base+simm9, using
EL0 privileges when at EL1.

10、Load-Acquire / Store-Release

 - LDAR Wt, [base{,#0}]

Load-Acquire Register: loads a word from memory addressed
 by base to Wt.

 - LDAR Xt, [base{,#0}]

Load-Acquire Register (extended): loads a doubleword from
 memory addressed by base to Xt.

 - LDARB Wt, [base{,#0}]

Load-Acquire Byte: loads a byte from memory addressed by
 base, then zero-extends it into Wt.

 - LDARH Wt, [base{,#0}]

Load-Acquire Halfword: loads a halfword from memory
 addressed by base, then zero-extends it into Wt.

 - STLR Wt, [base{,#0}]

Store-Release Register: stores a word from Wt to memory
 addressed by base.

 - STLR Xt, [base{,#0}]

Store-Release Register (extended): stores a doubleword
 from Xt to memory addressed by base.

 - STLRB Wt, [base{,#0}]

Store-Release Byte: stores a byte from Wt to memory 
addressed by base.

 - STLRH Wt, [base{,#0}]

Store-Release Halfword: stores a halfword from Wt to 
memory addressed by base.

 - LDAXR Wt, [base{,#0}]

Load-Acquire Exclusive Register: loads word from memory 
addressed by base to Wt. Records the
physical address as an exclusive access.

 - LDAXR Xt, [base{,#0}]

Load-Acquire Exclusive Register (extended): loads 
doubleword from memory addressed by base to Xt.
Records the physical address as an exclusive access.

 - LDAXRB Wt, [base{,#0}]

Load-Acquire Exclusive Byte: loads byte from memory 
addressed by base, then zero-extends it into Wt.
Records the physical address as an exclusive access.

 - LDAXRH Wt, [base{,#0}]

Load-Acquire Exclusive Halfword: loads halfword from 
memory addressed by base, then zero-extends it
into Wt. Records the physical address as an exclusive access.

 - LDAXP Wt, Wt2, [base{,#0}]

Load-Acquire Exclusive Pair Registers: loads two words 
from memory addressed by base to Wt and Wt2.
Records the physical address as an exclusive access.

 - LDAXP Xt, Xt2, [base{,#0}]

Load-Acquire Exclusive Pair Registers (extended): loads 
two doublewords from memory addressed by
base to Xt and Xt2. Records the physical address as an 
exclusive access.

 - STLXR Ws, Wt, [base{,#0}]

Store-Release Exclusive Register: stores word from Wt to 
memory addressed by base, and sets Ws to
the returned exclusive access status.

 - STLXR Ws, Xt, [base{,#0}]

Store-Release Exclusive Register (extended): stores 
doubleword from Xt to memory addressed by base,
and sets Ws to the returned exclusive access status.

 - STLXRB Ws, Wt, [base{,#0}]

Store-Release Exclusive Byte: stores byte from Wt to 
memory addressed by base, and sets Ws to the
returned exclusive access status.

 - STLXRH Ws, Xt|Wt, [base{,#0}]

Store-Release Exclusive Halfword: stores the halfword from 
Wt to memory addressed by base, and sets
Ws to the returned exclusive access status.

 - STLXP Ws, Wt, Wt2, [base{,#0}]

Store-Release Exclusive Pair: stores two words from Wt and 
Wt2 to memory addressed by base, and
sets Ws to the returned exclusive access status.

 - STLXP Ws, Xt, Xt2, [base{,#0}]

Store-Release Exclusive Pair (extended): stores two 
doublewords from Xt and Xt2 to memory addressed
by base, and sets Ws to the returned exclusive access status.

11、Prefetch Memory

**Arithmetic (immediate)**

 - ADD Wd|WSP, Wn|WSP, #aimm

Add (immediate): Wd|WSP = Wn|WSP + aimm.

 - ADD Xd|SP, Xn|SP, #aimm

Add (extended immediate): Xd|SP = Xn|SP + aimm.

 - ADDS Wd, Wn|WSP, #aimm

Add and set flags (immediate): Wd = Wn|WSP + aimm, setting 
the condition flags.

 - ADDS Xd, Xn|SP, #aimm

Add and set flags (extended immediate): Xd = Xn|SP + aimm,
 setting the condition flags.

 - SUB Wd|WSP, Wn|WSP, #aimm

Subtract (immediate): Wd|WSP = Wn|WSP - aimm.

 - SUB Xd|SP, Xn|SP, #aimm

Subtract (extended immediate): Xd|SP = Xn|SP - aimm.

 - SUBS Wd, Wn|WSP, #aimm

Subtract and set flags (immediate): Wd = Wn|WSP - aimm, 
setting the condition flags.

 - SUBS Xd, Xn|SP, #aimm

Subtract and set flags (extended immediate): Xd = Xn|SP - aimm, 
setting the condition flags.

 - CMP Wn|WSP, #aimm

Compare (immediate): alias for SUBS WZR,Wn|WSP,#aimm.

 - CMP Xn|SP, #aimm

Compare (extended immediate): alias for SUBS 
XZR,Xn|SP,#aimm.

 - CMN Wn|WSP, #aimm

Compare negative (immediate): alias for ADDS 
WZR,Wn|WSP,#aimm.

 - CMN Xn|SP, #aimm

Compare negative (extended immediate): alias for ADDS
 XZR,Xn|SP,#aimm.

 - MOV Wd|WSP, Wn|WSP

Move (register): alias for ADD Wd|WSP,Wn|WSP,#0, but only
 when one or other of the registers is WSP. 
 In other cases the ORR Wd,WZR,Wn instruction is used.

 - MOV Xd|SP, Xn|SP

Move (extended register): alias for ADD Xd|SP,Xn|SP,#0, 
but only when one or other of the registers is SP. 
In other cases the ORR Xd,XZR,Xn instruction is used.

**Logical (immediate)**

 - AND Wd|WSP, Wn, #bimm32

Bitwise AND (immediate): Wd|WSP = Wn AND bimm32.

 - AND Xd|SP, Xn, #bimm64

Bitwise AND (extended immediate): Xd|SP = Xn AND bimm64.

 - ANDS Wd, Wn, #bimm32

Bitwise AND and Set Flags (immediate): Wd = Wn AND bimm32, 
setting N & Z condition flags based on
the result and clearing the C & V flags.

 - ANDS Xd, Xn, #bimm64

Bitwise AND and Set Flags (extended immediate): Xd = Xn AND bimm64, 
setting N & Z condition flags based on the result and 
clearing the C & V flags.

 - EOR Wd|WSP, Wn, #bimm32

Bitwise exclusive OR (immediate): Wd|WSP = Wn EOR bimm32.

 - EOR Xd|SP, Xn, #bimm64

Bitwise exclusive OR (extended immediate): Xd|SP = Xn EOR bimm64.

 - ORR Wd|WSP, Wn, #bimm32

Bitwise inclusive OR (immediate): Wd|WSP = Wn OR bimm32.

 - ORR Xd|SP, Xn, #bimm64

Bitwise inclusive OR (extended immediate): Xd|SP = Xn OR bimm64.

 - MOVI Wd, #bimm32

Move bitmask (immediate): alias for ORR Wd,WZR,#bimm32,
 but may disassemble as MOV, see below.

 - MOVI Xd, #bimm64

Move bitmask (extended immediate): alias for ORR 
Xd,XZR,#bimm64, but may disassemble as MOV, see
below.

 - TST Wn, #bimm32

Bitwise test (immediate): alias for ANDS WZR,Wn,#bimm32.

 - TST Xn, #bimm64

Bitwise test (extended immediate): alias for ANDS XZR,Xn,#bimm64

**Move (wide immediate)**

 - MOVZ Wt, #uimm16{, LSL #pos}

Move with Zero (immediate): Wt = LSL(uimm16, pos).
Usually disassembled as MOV, see below.

 - MOVZ Xt, #uimm16{, LSL #pos}

Move with Zero (extended immediate): Xt = LSL(uimm16, pos).
Usually disassembled as MOV, see below.

 - MOVN Wt, #uimm16{, LSL #pos}

Move with NOT (immediate): Wt = NOT(LSL(uimm16, pos)).
Usually disassembled as MOV, see below.

 - MOVN Xt, #uimm16{, LSL #pos}

Move with NOT (extended immediate): Xt = NOT(LSL(uimm16, pos)).
Usually disassembled as MOV, see below.

 - MOVK Wt, #uimm16{, LSL #pos}

Move with Keep (immediate): Wt<pos+15:pos> = uimm16.

 - MOVK Xt, #uimm16{, LSL #pos}

Move with Keep (extended immediate): Xt<pos+15:pos> = uimm16.

**Move (immediate)**
MOV Wd, #simm32
A synthetic assembler instruction which generates a single 
MOVZ, MOVN or MOVI instruction that loads a
32-bit immediate value into register Wd. An assembler 
error shall result if the immediate cannot be created
by a single one of these instructions. If there is a 
choice, then to ensure reversability an assembler must
prefer a MOVZ to MOVN, and MOVZ or MOVN to MOVI. A 
disassembler may output MOVI, MOVZ and MOVN
as a MOV mnemonic, except when MOVI has an immediate that
 could be generated by a MOVZ or MOVN instruction, 
 or where a MOVN has an immediate that could be encoded by 
 MOVZ, or where MOVZ/MOVN #0 have a shift amount other than LSL #0, 
 in which case the machine-instruction mnemonic must be used.

 - MOV Xd, #simm64

As MOV but for loading a 64-bit immediate into register Xd.

12、Address Generation

 - ADRP Xd, label

Address of Page: sign extends a 21-bit offset, shifts it 
left by 12 and adds it to the value of the PC with its
bottom 12 bits cleared, writing the result to register Xd. 
This computes the base address of the 4KiB aligned memory region 
containing label, and is designed to be used in conjunction with a load, store or
ADD instruction which supplies the bottom 12 bits of the label’s address. 
This permits positionindependent addressing of any location 
within ±4GiB of the PC using two instructions, providing 
that dynamic relocation is done with a minimum granularity of 4KiB
 (i.e. the bottom 12 bits of the label’s address are 
 unaffected by the relocation). The term “page” is short-
 hand for the 4KiB relocation granule,and is not necessarily 
 related to the virtual memory page size.

 - ADR Xd, label

Address: adds a 21-bit signed byte offset to the program 
counter, writing the result to register Xd. Used to
compute 
the effective address of any location within ±1MiB of the PC

13、Bitfield Operations

 - BFM Wd, Wn, #r, #s

Bitfield Move: if s>=r then Wd<s-r:0> = Wn<s:r>, else 
Wd<32+s-r,32-r> = Wn<s:0>.Leaves other bits in Wd unchanged.

 - BFM Xd, Xn, #r, #s

Bitfield Move: if s>=r then Xd<s-r:0> = Xn<s:r>, else
 Xd<64+s-r,64-r> = Xn<s:0>.Leaves other bits in Xd unchanged.

 - SBFM Wd, Wn, #r, #s

Signed Bitfield Move: if s>=r then Wd<s-r:0> = Wn<s:r>, 
else Wd<32+s-r,32-r> = Wn<s:0>.Sets bits to the left of 
the destination bitfield to copies of its leftmost bit,
 and bits to the right to zero.

 - SBFM Xd, Xn, #r, #s

Signed Bitfield Move: if s>=r then Xd<s-r:0> = Xn<s:r>, else 
Xd<64+s-r,64-r> = Xn<s:0>. Sets bits to the left of the
 destination bitfield to copies of its leftmost bit, 
 and bits to the right to zero.

 - UBFM Wd, Wn, #r, #s

Unsigned Bitfield Move: if s>=r then Wd<s-r:0> = Wn<s:r>,
 else Wd<32+s-r,32-r> = Wn<s:0>.Sets bits to the left and right
  of the destination bitfield to zero.

 - UBFM Xd, Xn, #r, #s

Unsigned Bitfield Move: if s>=r then Xd<s-r:0> = Xn<s:r>, 
else Xd<32+s-r,32-r> = Xn<s:0>. Sets bits to the left and
 right of the destination bitfield to zero.

 - BFI Wd, Wn, #lsb, #width

Bitfield Insert: alias for BFM Wd,Wn,#((32-lsb)&31),#(width-1).
Preferred for disassembly when s < r.

 - BFI Xd, Xn, #lsb, #width

Bitfield Insert (extended): alias for BFM Xd,Xn,#((64-lsb)&63),#(width-1).
Preferred for disassembly when s < r.

 - BFXIL Wd, Wn, #lsb, #width

Bitfield Extract and Insert Low: alias for BFM Wd,Wn,#lsb,#(lsb+width-1).
Preferred for disassembly when s >= r.

 - BFXIL Xd, Xn, #lsb, #width

Bitfield Extract and Insert Low (extended): alias for BFM Xd,Xn,#lsb,#(lsb+width-1).
Preferred for disassembly when s >= r.

 - SBFIZ Wd, Wn, #lsb, #width

Signed Bitfield Insert in Zero: alias for) SBFM Wd,Wn,#((32-lsb)&31),#(width-1).
Preferred for disassembly when s < r.

 - SBFIZ Xd, Xn, #lsb, #width

Signed Bitfield Insert in Zero (extended): alias for SBFM Xd,Xn,#((64-lsb)&63),#(width-1).
Preferred for disassembly when s < r.

 - SBFX Wd, Wn, #lsb, #width

Signed Bitfield Extract: alias for SBFM Wd,Wn,#lsb,#(lsb+width-1).
Preferred for disassembly when s >= r.

 - SBFX Xd, Xn, #lsb, #width

Signed Bitfield Extract (extended): alias for SBFM Xd,Xn,#lsb,#(lsb+width-1).
Preferred for disassembly when s >= r.

 - UBFIZ Wd, Wn, #lsb, #width

Unsigned Bitfield Insert in Zero: alias for UBFM Wd,Wn,#((32-lsb)&31),#(width-1).
Preferred for disassembly when s < r.

 - UBFIZ Xd, Xn, #lsb, #width

Unsigned Bitfield Insert in Zero (extended): alias for UBFM Xd,Xn,#((64-lsb)&63),#(width-1).
Preferred for disassembly when s < r.

 - UBFX Wd, Wn, #lsb, #width

Unsigned Bitfield Extract: alias for UBFM Wd,Wn,#lsb,#(lsb+width-1).
Preferred for disassembly when s >= r.

 - UBFX Xd, Xn, #lsb, #width

Unsigned Bitfield Extract (extended): alias for UBFM Xd,Xn,#lsb,#(lsb+width-1).
Preferred for disassembly when s >= r.

14、Extract (immediate)

 - EXTR Wd, Wn, Wm, #lsb

Extract: Wd = Wn:Wm<lsb+31,lsb>. The bit position lsb must be in the range 0 to 31.

 - EXTR Xd, Xn, Xm, #lsb

Extract (extended): Xd = Xn:Xm<lsb+63,lsb>. The bit position lsb must be in the range
 0 to 63.

15、Shift (immediate)

 - ASR Wd, Wn, #uimm

Arithmetic Shift Right (immediate): alias for SBFM Wd,Wn,#uimm,#31.

 - ASR Xd, Xn, #uimm

Arithmetic Shift Right (extended immediate): alias for SBFM Xd,Xn,#uimm,#63.

 - LSL Wd, Wn, #uimm

Logical Shift Left (immediate): alias for UBFM Wd,Wn,#((32-uimm)&31),#(31-uimm).

 - LSL Xd, Xn, #uimm

Logical Shift Left (extended immediate): alias for UBFM Xd,Xn,#((64-uimm)&63),
#(63-uimm)

 - LSR Wd, Wn, #uimm

Logical Shift Left (immediate): alias for UBFM Wd,Wn,#uimm,#31.

 - LSR Xd, Xn, #uimm

Logical Shift Left (extended immediate): alias for UBFM Xd,Xn,#uimm,#31.

 - ROR Wd, Wm, #uimm

Rotate Right (immediate): alias for EXTR Wd,Wm,Wm,#uimm.

 - ROR Xd, Xm, #uimm

Rotate Right (extended immediate): alias for EXTR Xd,Xm,Xm,#uimm.

16、Sign/Zero Extend

 - SXT[BH] Wd, Wn

Signed Extend Byte|Halfword: alias for SBFM Wd,Wn,#0,#7|15.

 - SXT[BHW] Xd, Wn

Signed Extend Byte|Halfword|Word (extended): alias for SBFM Xd,Xn,#0,#7|15|31.

 - UXT[BH] Wd, Wn

Unsigned Extend Byte|Halfword: alias for UBFM Wd,Wn,#0,#7|15.

 - UXT[BHW] Xd, Wn

Unsigned Extend Byte|Halfword|Word (extended): alias for UBFM Xd,Xn,#0,#7|15|31.

17、Data Processing (register)

**Arithmetic (shifted register)**

 - ADD Wd, Wn, Wm{, ashift #imm}

Add (register): Wd = Wn + ashift(Wm, imm).

 - ADD Xd, Xn, Xm{, ashift #imm}

Add (extended register): Xd = Xn + ashift(Xm, imm).

 - ADDS Wd, Wn, Wm{, ashift #imm}

Add and Set Flags (register): Wd = Wn + ashift(Wm, imm), setting condition flags.

 - ADDS Xd, Xn, Xm{, ashift #imm}

Add and Set Flags (extended register): Xd = Xn + ashift(Xm, imm), 
setting condition flags.

 - SUB Wd, Wn, Wm{, ashift #imm}

Subtract (register): Wd = Wn - ashift(Wm, imm).

 - SUB Xd, Xn, Xm{, ashift #imm}

Subtract (extended register): Xd = Xn - ashift(Xm, imm).

 - SUBS Wd, Wn, Wm{, ashift #imm}

Subtract and Set Flags (register): Wd = Wn - ashift(Wm, imm), 
setting condition flags.

 - SUBS Xd, Xn, Xm{, ashift #imm}

Subtract and Set Flags (extended register): Xd = Xn - ashift(Xm, imm), 
setting condition flags.

 - CMN Wn, Wm{, ashift #imm}

Compare Negative (register): alias for ADDS WZR, Wn, Wm{, ashift #imm}.

 - CMN Xn, Xm{, ashift #imm}

Compare Negative (extended register): alias for ADDS XZR, Xn, Xm{, ashift #imm}.

 - CMP Wn, Wm{, ashift #imm}

Compare (register): alias for SUBS WZR, Wn, Wm{,ashift #imm}.

 - CMP Xn, Xm{, ashift #imm}

Compare (extended register): alias for SUBS XZR, Xn, Xm{, ashift #imm}.

 - NEG Wd, Wm{, ashift #imm}

Negate: alias for SUB Wd, WZR, Wm{, ashift #imm}.

 - NEG Xd, Xm{, ashift #imm}

Negate (extended): alias for SUB Xd, XZR, Xm{, ashift #imm}.

 - NEGS Wd, Wm{, ashift #imm}

Negate and Set Flags: alias for SUBS Wd, WZR, Wm{, ashift #imm}.

 - NEGS Xd, Xm{, ashift #imm}

Negate and Set Flags (extended): alias for SUBS Xd, XZR, Xm{, ashift #imm}.

**Arithmetic (extending register)**

 - ADD Wd|WSP, Wn|WSP, Wm, extend {#imm}

Add (register, extending): Wd|WSP = Wn|WSP + LSL(extend(Wm),imm).

 - ADD Xd|SP, Xn|SP, Wm, extend {#imm}

Add (extended register, extending): Xd|SP = Xn|SP + LSL(extend(Wm),imm).

 - ADD Xd|SP, Xn|SP, Xm{, UXTX|LSL #imm}

Add (extended register, extending): Xd|SP = Xn|SP + LSL(Xm,imm).

 - ADDS Wd, Wn|WSP, Wm, extend {#imm}

Add and Set Flags (register, extending): Wd = Wn|WSP + LSL(extend(Wm),imm), 
setting the condition flags.

 - ADDS Xd, Xn|SP, Wm, extend {#imm}

Add and Set Flags (extended register, extending): Xd = Xn|SP + LSL(extend(Wm),imm),
 setting the condition flags.

 - ADDS Xd, Xn|SP, Xm{, UXTX|LSL #imm}

Add and Set Flags (extended register, extending): Xd = Xn|SP + LSL(Xm,imm),
 setting the condition flags.

 - SUB Wd|WSP, Wn|WSP, Wm, extend {#imm}

Subtract (register, extending): Wd|WSP = Wn|WSP - LSL(extend(Wm),imm).

 - SUB Xd|SP, Xn|SP, Wm, extend {#imm}

Subtract (extended register, extending): Xd|SP = Xn|SP - LSL(extend(Wm),imm).

 - SUB Xd|SP, Xn|SP, Xm{, UXTX|LSL #imm}

Subtract (extended register, extending): Xd|SP = Xn|SP - LSL(Xm,imm).

 - SUBS Wd, Wn|WSP, Wm, extend {#imm}

Subtract and Set Flags (register, extending): Wd = Wn|WSP - LSL(extend(Wm),imm), 
setting the condition flags.

 - SUBS Xd, Xn|SP, Wm, extend {#imm}

Subtract and Set Flags (extended register, extending): Xd = Xn|SP - LSL(extend(Wm),imm),
setting the condition flags.

 - SUBS Xd, Xn|SP, Xm{, UXTX|LSL #imm}

Subtract and Set Flags (extended register, extending): Xd = Xn|SP - LSL(Xm,imm), 
setting the condition flags.

 - CMN Wn|WSP, Wm, extend {#imm}

Compare Negative (register, extending): alias for ADDS WZR,Wn,Wm,extend {#imm}.

 - CMN Xn|SP, Wm, extend {#imm}

Compare Negative (extended register, extending): alias for ADDS XZR,Xn,Wm,extend {#imm}.

 - CMN Xn|SP, Xm{, UXTX|LSL #imm}

Compare Negative (extended register, extending): alias for ADDS XZR,Xn,Xm{,UXTX|LSL #imm}.

 - CMP Wn|WSP, Wm, extend {#imm}

Compare (register, extending): alias for SUBS WZR,Wn,Wm,extend {#imm}.

 - CMP Xn|SP, Wm, extend {#imm}

Compare (extended register, extending): alias for SUBS XZR,Xn,Wm,extend {#imm}.

 - CMP Xn|SP, Xm{, UXTX|LSL #imm}

Compare (extended register, extending): alias for SUBS XZR,Xn,Xm{,UXTX|LSL #imm}