Intel CMT & CAT & CDP 技術
Intel Cache Monitoring Technology (CMT) and Cache Allocation Technology (CAT)
查看當前系統 L3 cache 詳情
pqos -v
NOTE: Mixed use of MSR and kernel interfaces to manage
CAT or CMT & MBM may lead to unexpected behavior.
INFO: CACHE: type 1, level 1, max id sharing this cache 2 (1 bits)
INFO: CACHE: type 2, level 1, max id sharing this cache 2 (1 bits)
INFO: CACHE: type 3, level 2, max id sharing this cache 2 (1 bits)
INFO: CACHE: type 3, level 3, max id sharing this cache 32 (5 bits)
INFO: Monitoring capability detected
INFO: CPUID.0x7.0: L3 CAT supported
INFO: CDP is disabled
INFO: L3 CAT details: CDP support=1, CDP on=0, #COS=16, #ways=20, ways contention bit-mask 0xc0000
INFO: L3 CAT details: cache size 26214400 bytes, way size 1310720 bytes
INFO: L3CA capability detected
INFO: CPUID 0x10.0: L2 CAT not supported!
INFO: L2CA capability not detected
INFO: CPUID 0x10.0: MBA not supported!
INFO: MBA capability not detected
INFO: resctrl not detected. Kernel version 4.10 or higher required
INFO: OS support for CMT detected
INFO: OS support for L3 CAT not detected
INFO: resctrl not mounted
WARN: Hijacking performance counters on core 0
WARN: Hijacking performance counters on core 1
WARN: Hijacking performance counters on core 2
WARN: Hijacking performance counters on core 3
WARN: Hijacking performance counters on core 4
WARN: Hijacking performance counters on core 5
WARN: Hijacking performance counters on core 6
WARN: Hijacking performance counters on core 7
WARN: Hijacking performance counters on core 8
WARN: Hijacking performance counters on core 9
WARN: Hijacking performance counters on core 10
WARN: Hijacking performance counters on core 11
WARN: Hijacking performance counters on core 12
WARN: Hijacking performance counters on core 13
WARN: Hijacking performance counters on core 14
WARN: Hijacking performance counters on core 15
WARN: Hijacking performance counters on core 16
WARN: Hijacking performance counters on core 17
WARN: Hijacking performance counters on core 18
WARN: Hijacking performance counters on core 19
TIME 2017-08-15 17:51:52
CORE IPC MISSES LLC[KB] MBL[MB/s] MBR[MB/s]
0 0.44 27k 0.0 0.0 0.0
1 0.73 0k 0.0 0.0 0.0
2 5.46 0k 0.0 0.0 0.0
3 5.46 0k 0.0 0.0 0.0
4 5.46 0k 0.0 0.0 0.0
5 2.77 2k 40.0 0.0 0.0
6 0.53 196k 560.0 0.0 0.0
7 1.35 238k 760.0 0.0 0.0
8 0.37 0k 0.0 0.0 0.0
9 0.37 0k 0.0 0.0 0.0
10 0.32 0k 0.0 0.0 0.0
11 0.38 0k 0.0 0.0 0.0
12 0.32 0k 0.0 0.0 0.0
13 0.32 0k 0.0 0.0 0.0
14 0.29 0k 0.0 0.0 0.0
15 0.26 0k 0.0 0.0 0.0
16 0.37 0k 0.0 0.0 0.0
17 0.37 0k 0.0 0.0 0.0
18 0.33 0k 0.0 0.0 0.0
19 0.34 0k 0.0 0.0 0.0
pqos -s
NOTE: Mixed use of MSR and kernel interfaces to manage
CAT or CMT & MBM may lead to unexpected behavior.
L3CA COS definitions for Socket 0:
L3CA COS0 => MASK 0xfffff
...
L3CA COS definitions for Socket 1:
L3CA COS0 => MASK 0xfffff
...可知當前系統支持CDP, L3 Cache 25M, way 大小 1310720 , 總計 20 ways.
L3 CAT details: CDP support=1, CDP on=0, #COS=16, #ways=20, ways contention bit-mask 0xc0000
INFO: L3 CAT details: cache size 26214400 bytes, way size 1310720 默認所有core使用所有的 L3 cache way
配置 L3 cache 分配策略(1使用4-way,2使用16-way)
pqos -e "llc:1=0x000f;llc:2=0xffff0;"配置 L3 cache 分配策略(1使用2-way,2使用14-way,3使用4-way)
pqos -e "llc:1=0x00003;llc:2=0xfffc0;llc:3=0x0003c"配置 CPU core L3 cache 分配策略
pqos -a "llc:1=0,21;llc:2=1-4,6-9,11-14,16-19;llc:3=5,10,15,20"
sudo pqos -e llc:1=0x0001
sudo pqos -a llc:1=0
sudo taskset -apc 0 $(pidof qemu-system-x86_64)
sudo pqos -e "llc:2=0x0ffe"
sudo pqos -a "llc:2=1-11"注意:
只有Intel v3部分 & v4 系列CPU支持 CDP. 此功能主要用於優化虛擬機 & DPDK 等應用場景，減少cache miss, 提高性能.
參考
INTEL® XEON® PROCESSOR E5 FAMILY
Intel® Xeon® Processor E5-2600 v4 Product Family
Intel Resource Director Technology
Introduction to Cache Allocation Technology in the Intel® Xeon® Processor E5 v4 Family
Usage Models for Cache Allocation Technology in the Intel® Xeon® Processor E5 v4 Family
Software Enabling for Cache Allocation Technology in the Intel® Xeon® Processor E5 v4 Family
Proof Points for Cache Allocation Technology in the Intel® Xeon® Processor E5 v4 Family
Proof Points: Memory Bandwidth Monitoring in the Intel® Xeon® Processor E5 v4 Family
Code and Data Prioritization - Introduction and Usage Models in the Intel® Xeon® Processor E5 v4 Family
Intel-CMT-CAT Usage Examples
Understanding NUMA for 3D isotropic Finite Difference (3DFD) wave equation code
Web Resources about Intel® Transactional Synchronization Extensions
Intel Platform Quality of Service and Cache Allocation Technology
http://kernel.ubuntu.com/~cking/stress-ng/
https://github.com/01org/intel-cmt-cat/wiki/Useful-links
https://software.intel.com/en-us/articles/intel-performance-counter-monitor
https://www.kernel.org/doc/Documentation/x86/intel_rdt_ui.txt
https://software.intel.com/en-us/search/site/language/en?query=Cache+Allocation+Technology+in+the+Intel%C2%AE+Xeon%C2%AE+Processor+E5+v4+Family
http://danluu.com/intel-cat/
https://software.intel.com/en-us/articles/intel-xeon-processor-e5-2600-v4-product-family-technical-overview