FPGA按鍵和閃燈

三個按鍵和四個燈，前三個按鍵控制前三個燈的反轉，最後一個燈1s反轉一次。

只有一個key模塊爲主模塊

module key
(
	input clk,//輸入時鐘50M
	input rst_n,//復位
	input [2:0]keyin,//3個按鍵輸入
	output reg [3:0]led=0//四個led輸出
);

reg[31:0]counter=0;//計數到達1s
reg[19:0]counter2=0;//計數達到20ms
reg clk_1hz=0;
reg [2:0]key;//當前輸入按鍵
reg [2:0]key_past;//之前的輸入按鍵
wire [2:0]key_flag=key_past[2:0]&(~key[2:0]);//判斷按鍵的下降沿

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
			counter<=0;
		else if(counter==32'd49999999)
			counter<=0;
		else
			counter<=counter+1'b1;
end

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
			counter2<=0;
		else if(counter2==20'd999999)
			begin counter2<=0;key<=keyin;end//20ms簡單濾除毛刺
		else
			counter2<=counter2+1'b1;
end

always@(posedge clk)
begin
	key_past<=key;
end

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
			clk_1hz<=0;
		else if(counter==32'd24999999)
			clk_1hz<=1;
		else if(counter==32'd49999999)
			clk_1hz<=0;
end


always@(posedge clk_1hz or negedge rst_n)
begin
	if(~rst_n)
		led[3]<=0;
	else 
		led[3]<=~led[3];
end

always@(posedge clk or negedge rst_n)
begin
	if(~rst_n)
		led[2:0]<=0;
	else
		begin
			if(key_flag[2]==1)
				led[2]<=~led[2];
			if(key_flag[1]==1)
				led[1]<=~led[1];
			if(key_flag[0]==1)
				led[0]<=~led[0];
		end
end

endmodule