CPU模式（mode）、狀態與寄存器

ARM920T的7種工作模式

（1）usr：正常模式

（2）sys：系統

（3）異常模式

• und：未定義模式
• svc：管理模式
• abt：中止模式：

1. 指令預取
2. 數據訪問

• irq：中斷模式
• fiq：快中斷模式

2種狀態

（1）ARM指令集

每條指令佔用4字節

（2）thumb指令集

每條指令佔用2字節

比如指令 mov r0, r1使用不同指令集編譯後，每條指令佔用的空間大小不同

1. ARM：4byte機器碼
2. THUMB：2byte機器碼

寄存器

（1）我們可以看到在異常情況下的寄存器有些事帶有灰色的三角，表明在這幾種異常模式下，這幾個寄存器是有別的用處

其中r13還是我們常說的sp寄存器；r14就是lr寄存器，保存放回的地址

（2）下面是當前狀態寄存器（CPSR）每一位的含義

（3）而異常模式下還有一個SPSR，就是用來保存用戶模式下的CPSR的值

ARM手冊上的簡單異常處理流程描述

Action on Entering an Exception（進入異常模式的幾個動作）
While handling an exception, the ARM920T does following activities:
1. Preserves the address of the next instruction in the appropriate Link Register（LR_異常 = 下一個PC+4或者+8）. If the exception has been
entered from ARM state, then the address of the next instruction is copied into the Link Register (that is,
current PC + 4 or PC + 8 depending on the exception. See Table 2-2 on for details). If the exception has been
entered from THUMB state, then the value written into the Link Register is the current PC offset by a value
such that the program resumes from the correct place on return from the exception. This means that the
exception handler need not determine which state the exception was entered from. For example, in the case of
SWI, MOVS PC, R14_svc will always return to the next instruction regardless of whether the SWI was
executed in ARM or THUMB state.
2. Copies the CPSR into the appropriate SPSR
3. Forces the CPSR mode bits to a value which depends on the exception
4. Forces the PC to fetch the next instruction from the relevant exception vector
It may also set the interrupt disable flags to prevent otherwise unmanageable nestings of exceptions.
If the processor is in THUMB state when an exception occurs, it will automatically switch into ARM state when the

PC is loaded with the exception vector address.

Action on Leaving an Exception（離開異常模式的幾個動作）
On completion, the exception handler:
1. Moves the Link Register, minus an offset where appropriate, to the PC. (The offset will vary depending on the
type of exception.)
2. Copies the SPSR back to the CPSR
3. Clears the interrupt disable flags, if they were set on entry