Older versions of the ARM architecture enabled implementers considerable freedom in the design of an external interrupt controller, with no agreement over the number or types of interrupts or the software model to be used to interface to the interrupt controller block.
在外部中斷控制器的設計中舊版本的ARM架構的實現能夠很自由,沒有在中斷控制器的中斷或軟件模型的數量或類型限制的協議接口。
The Generic Interrupt Controller v2 (GIC) architecture provides a much moretightly controlled specification, with a greater degree of consistency between interrupt controllers from different manufacturers.
通用中斷控制器 v2(GIC)體系結構提供了更嚴格的控制規範,以更大程度的使來自不同製造商的中斷控制器之間的一致性。
This enables interrupt handler code to be more portable.
這使中斷處理程序代碼移植性更高。
12.1 External interrupt requests
12.1外部中斷請求
Types of exceptionon page 11-3, described how all ARM cores have two external interrupt requests, FIQ and IRQ.
如11-3所述,所有ARM內核有兩個外部中斷請求FIQ和IRQ。
Both of these are level-sensitive active-LOW inputs.
這兩個都是低電平有效。
Individual implementations have interrupt controllers that accept interrupt requests from a wide variety of external sources and map them onto FIQ or IRQ, causing the core to take an exception.
個人實現的中斷控制器接受來自各種外部中斷請求並將它們映射到FIQ或硬中斷請求優先級別,導致核心帶一個例外。
In general, an interrupt exception can be taken only when the appropriate CPSR disable bit (the F and I bits respectively) is clear and if the corresponding input is asserted.
一般來說,一箇中斷異常可以只有當適當的CPSR禁用一些(F和我分別位)是明確的,如果相應的輸入是斷言。
The CPSinstruction provides a simple mechanism to enable or disable the exceptions controlled
CPSinstruction提供了一種簡單的機制來啓用或禁用控制異常
by CPSR A, I and F bits (asynchronous abort, IRQ and FIQ respectively).
通過CPSR,我和F(異步中止,硬中斷請求優先級別和FIQ分別)。
IEor CPS IDwill enable or disable exceptions respectively.
分別IEor CPS IDwill啓用或禁用例外。
The exceptions to be enabled or disabled are specified using one or more of the letters A, I and F. Exceptions whose corresponding letters are omitted will not be modified.
啓用或禁用的異常指定使用一個或多個字母A,i和f .異常的相應字母省略了不會被修改。
In Cortex-A series processors, it is possible to configure the core so that FIQs cannot be masked by software.
Cortex-A系列處理器,可以配置的核心,因此FIQs無法掩蓋的軟件。
This is known as Non-Maskable FIQ and is controlled by a hardware configuration input signal that is sampled when the core is reset.
這被稱爲屏敝FIQ由硬件配置和控制輸入信號採樣時,核心是重置。
They will still be masked automatically on taking an FIQ exception.
他們仍將蒙面自動FIQ例外。
12.1.1 Assigning interrupts
12.1.1分配中斷
A system will always have an interrupt controller that accepts and arbitrates interrupts from multiple sources.
系統將總是有一箇中斷控制器接受來自多個來源,斷定中斷。
This typically contains a number of registers enabling software running on the core to mask individual interrupt sources, to acknowledge interrupts from external devices, to assign priorities to individual interrupt sources and to determine which interrupt sources are currently requesting attention or require servicing.
這通常包含許多寄存器使軟件運行在覈心面具個人中斷源,承認從外部設備中斷,將優先分配給個人中斷源和確定哪些中斷源目前請求關注或者需要維修。
This interrupt controller can be a design specific to the system, or it can be an implementation of the ARM Generic Interrupt Controller(GIC) architecture, described in The Generic Interrupt Controlleron page 12-7.
這個中斷控制器可以設計特定的系統,也可以是一個實現手臂的通用的中斷控制器(GIC)的體系結構,描述的通用的中斷12-7 Controlleron頁面。
12.1.2 Simplistic interrupt handling
12.1.2簡單的中斷處理
This represents the simplest kind of interrupt handler.
這是最簡單的一種中斷處理程序。
On taking an interrupt, additional interrupts of the same kind are disabled until explicitly enabled later.
在一箇中斷,中斷的同樣被禁用,直到顯式地啓用後。
We can only handle additional interrupts at the completion of the first interrupt request and there is no scope for a higher priority or more urgent interrupt to behandled during this time.
我們只能處理額外的中斷在完成第一個中斷請求,沒有範圍更高的優先級或更緊急中斷behandled在這段時間。
This is not generally suitable for complex embedded systems, but it is useful to examine before proceeding to a more realistic example, in this case of a non re-entrant interrupt handler.
這不是一般適用於複雜的嵌入式系統,但它是有用的檢查之前,一個更實際的例子,在這個例子中,一個非凹角中斷處理程序。
The steps taken to handle aninterrupt are as follows:
處理aninterrupt採取的步驟如下:
1.An IRQ exception is raised by external hardware.
1.一個IRQ異常是由外部硬件。
The core performs several steps automatically.
核心自動執行幾個步驟。
The contents of the PC inthe current execution mode are stored in LR_IRQ.
電腦在當前執行模式的內容存儲在LR_IRQ。
The CPSR register is copied to SPSR_IRQ.
CPSR寄存器是SPSR_IRQ複製。
The CPSR content is updated so that the mode bits reflects the IRQ mode, and the I bit is set to mask additional IRQs.
CPSR內容中反映了IRQ模式的模式位被更新,並且 I 位設置成IRQs模式。
The PC is set to the IRQ entry in the vector table.
PC設置爲IRQ向量表中的條目。
2.The instruction at the IRQ entry in the vector table (a branch to the interrupt handler) is executed.
2.IRQ矢量表中的條目的指令執行中斷處理程序(分支)。
3.The interrupt handler saves the context of the interrupted program, that is, it pushes onto the stack any registers that will be corrupted by the handler.
3.中斷處理程序保存中斷程序的上下文中,也就是說,它推到堆棧寄存器將被處理。
These registers will be popped from stack when the handler finishes execution.
這些寄存器將從堆棧彈出當處理程序完成執行。
4.中斷源的中斷處理程序決定了必須被處理和調用適當的設備驅動程序。
5.Prepare the core to switch to previous execution state by copying the SPSR_IRQ to CPSR, and restoring the context saved earlier, and finally the PC is restored from LR_IRQ.
5.準備好的核心通過複製SPSR_IRQ CPSR 切換到先前的執行狀態,並且恢復之前保存的上下文,最後PC從LR_IRQ恢復。
A very simple interrupt handler is shown in Example 12-1.
一個非常簡單的中斷處理程序例子 12-1所示。
-------------------------------------------------------------------------------------IRQ_Handler
PUSH {r0-r3, r12, lr} @ Store AAPCS registers and LR onto the IRQ mode stack
BL @ identify_and_clear_source
BL @ C-irq_handler
POP {r0-r3, r12, lr} @ Restore registers and
SUBS pc, lr, #4 @ return from exception using modified LR
-------------------------------------------------------------------------------------
12.2 The Generic Interrupt Controller
12.2通用中斷控制器
The GIC architecture defines a Generic InterruptController (GIC) that comprises a set of hardware resources for managing interrupts in a single or multi-core system.
GIC體系結構定義了一個通用InterruptController(GIC)組成的一組硬件資源管理中斷在單一或多核系統。
The GIC provides memory-mapped registers that can be used to manage interrupt sources and behavior and (in multi-core systems) for routing interrupts to individual cores.
GIC提供了內存映射寄存器,可以用來管理中斷源和行爲和(在多核系統)個人核心路由中斷。
It enables software to mask, enable and disable interrupts from individual sources, to prioritize (in hardware) individual sources and to generate software interrupts.
它使軟件面具,從個人來源、啓用和禁用中斷優先級(硬件)個人來源和生成軟件中斷。
It also provides support for the TrustZone Security Extensions described in Chapter 21 Security.
它還提供了支持TrustZone安全擴展21章中描述的安全。
The GIC accepts interrupts asserted at the system level and can signal them to each core it is connected to, potentially resulting in an IRQ or FIQ exception being taken.
GIC接受中斷斷言在系統水平和能信號連接到每個核心,可能導致一個IRQ或FIQ異常。
From a software perspective, a GIC has two major functional blocks:
從軟件的角度來看,GIC有兩個主要功能模塊:
Distributor
分配器
to which all interrupt sources in the systemare wired.
所有systemare連線中斷源。
The distributor has registers to control the properties of individual interrupts such aspriority, state, security, routing information and enable status.
分配器寄存器來控制個體的屬性aspriority等中斷狀態,安全、路由信息和啓用狀態。
The distributor determines which interrupt is to be forwarded to a core, through the attachedCPU interface.
分配器確定哪些中斷轉發到一個核心,通過attachedCPU接口。
CPU Interface
CPU接口
through which a core receives an interrupt.
通過一個核心接收中斷。
The CPU interface hosts registers to mask, identify and control states of interrupts forwarded to that core.
主機CPU接口寄存器面具,識別和控制中斷的狀態轉發到核心。
There is a separate CPU interface for each core in the system.
有一個單獨爲每個核心系統中CPU接口。
Interrupts are identified in the software by a number, called an interrupt ID. An interrupt ID uniquely corresponds to an interrupt source.
中斷識別軟件的一個數字,稱爲一箇中斷ID。一箇中斷ID唯一地對應於一箇中斷源。
Software can use the interrupt ID to identify the source of interrupt and to invoke the corresponding handler to service the interrupt.
軟件可以使用中斷的中斷ID來識別來源並調用相應的服務中斷處理程序。
The exact interrupt ID presented to the software is determined by the system design,Interrupts can be of a number of different types:
準確的中斷ID提供給軟件由系統設計、中斷可以許多不同的類型:
Software Generated Interrupt (SGI)
軟件生成的中斷(SGI)
This is generated explicitly by software by writing to a dedicated distributor register, theSoftware Generated Interrupt Register(ICDSGIR).
這是由軟件生成的顯式地通過編寫專門的經銷商註冊,軟件生成的中斷寄存器(ICDSGIR)。
It is most commonly used for inter-core communication.
人性講堂是最常用的溝通。
SGIs can be targeted at all, or a selected group of cores inthe system.
可以針對所有SGIs,或一組被選的核心在系統。
Interrupt numbers 0-15 are reserved for this.
中斷數0-15保留。
The exact interrupt number used for communication is at the discretion of software.
準確的中斷號用於通信軟件的自由裁量權。
Private Peripheral Interrupt (PPI)
私人外設中斷(PPI)
This is generated by a peripheral that isprivate to an individual core.
這是由isprivate單個核心的外圍。
Interrupt numbers 16-31 are reserved for this.
中斷數16-31保留。
These identify interrupt sources private to the core, and is independent of the same source on another core, for example, per-core timer.
這些中斷源識別私人核心,是獨立的同一來源的另一個核心,例如,每個覈計時器。
Shared Peripheral Interrupt (SPI)
共享外圍中斷(SPI)
This is generated by a peripheral that the Interrupt Controllercan route to more than one core.
這是由外圍生成中斷Controllercan途徑不止一個核心。
Interrupt numbers 32-1020 are used for this.
中斷使用數字32 - 1020。
SPIs are used to signal interrupts from various peripherals accessible across the whole the system.
spi用於信號從各種外設中斷訪問整個系統。
Interrupts can either be edge-triggered (considered to be assertedwhen the Interrupt Controller detects a rising edge on the relevant input – and to remain asserted until cleared) or level-sensitive (considered to be asserted only when the relevant input to the Interrupt Controller is HIGH).
中斷可以是邊沿觸發(被認爲是assertedwhen中斷控制器檢測到一個前沿的相關輸入,宣稱將持續到清除)或level-sensitive(被認爲是斷言只有當相關的中斷控制器的輸入是高)。
An interrupt can be in a number of different states:
一箇中斷可以在許多不同的部分:
• Inactive– this means that the interrupt is not asserted yet.
•活動——這意味着中斷還沒有斷言。
• Pending– this means that the interrupt source has been asserted, but is waiting to be handled by a core.
•等待——這意味着中斷源已經斷言,但等待是由核心處理。
Pending interrupts are candidates to be forwarded to the CPU interface and then later on to the core.
等待中斷候選人被轉發到CPU接口和後來的核心。
• Active– this describes an interrupt that has been acknowledged by a core and is currently being serviced.
•積極——這描述了一箇中斷,承認了一個核心,目前正在維修。
• Active and pending– this describes the situation where a core is servicing the interrupt and the GIC also has a pending interrupt from the same source.
•積極和等待——這描述了情況的核心服務中斷,新加坡政府投資公司也有一個等待中斷從同一來源。
The priority and list of cores to which an interrupt can be delivered to are all configured in the distributor.
一箇中斷的優先級和內核列表可以交付給分銷商都配置。
An interrupt asserted to the distributor by a peripheral will be marked in Pending state (or Active and Pending if was already Active).
一箇中斷斷言外圍的分銷商將標記爲掛起狀態(或主動,等待如果已經主動)。
The distributor determines the highest priority pending interrupt that can be delivered to a core and forwards that to the CPU interface of the core.
經銷商確定最高優先級等待中斷可以送到一個核心和遠期的CPU接口的核心。
At the CPU interface, the interrupt is in turn signalled to the core, at which point the core takes the FIQ or IRQ exception.
在CPU接口、中斷是核心,依次表示此時核心FIQ或IRQ異常。
The core executes the exception handler in response.
核心執行異常處理程序。
The handler must query the interrupt ID from a CPU interface register and begin servicing the interrupt source.
中斷處理程序必須查詢ID從CPU接口註冊並開始維修中斷源。
12.2.1 Configuration
12.2.1配置
The GIC is accessed as a memory-mapped peripheral.
GIC是訪問內存映射外圍。
All cores can access the common distributor block, but the CPU interface is banked, that is, each core usesthe same address to access its own private CPU interface.
所有核心可以訪問常見的經銷商,但CPU接口是傾斜的,也就是說,每個核心採用相同的地址來訪問自己的私有CPU接口。
It is not possible for a coreto access the CPU interface of another core.
它是不可能coreto訪問另一個核心的CPU接口。
See Handling interrupts in an SMP systemon page 18-14for more details.
在SMP systemon頁面看到處理中斷18-14for更多細節。
The distributor hosts a number of registers thatyou can use to configure the properties of individual interrupts.
經銷商主機的註冊你可以使用配置屬性的個人中斷。
These configurable properties are:
這些可配置屬性:
• An interrupt priority.
•一箇中斷優先級。
The distributor uses this to determine which interrupt is next forwarded to the CPU interface.
中斷的經銷商使用這個來確定下一個轉發到CPU接口。
• An interrupt configuration.
•一箇中斷配置。
This determines if an interrupt is level- or edge-sensitive.
這決定了如果一箇中斷或edge-sensitive水平。
• An interrupt target.
•一箇中斷的目標。
This determines a list of cores to which an interrupt can be forwarded.
這決定了核心的列表可以轉發一箇中斷。
• Interrupt enable or disable status.
•中斷啓用或禁用狀態。
Only those interrupts that are enabled in the distributor are eligible to be forwarded when they become pending.
只有那些中斷中啓用的分銷商資格被轉發時變得懸而未決。
• Interrupt security determines whether the interrupt is allocated to Secure or Normal world software.
•中斷安全決定中斷分配給軟件安全或正常的世界。
• An Interrupt state.
•一箇中斷狀態。
The distributor also provides priority masking by which interrupts below a certain priority are prevented from reaching the core.
分配器還提供優先級屏蔽，低於一定的優先級的中斷是無法到達核心的。
The distributor uses this when determining whether a pending interrupt can be forwarded to a particular core.
分配器使用這個決定推遲中斷時可以轉發到一個特定的核心。
The CPU interfaces on each core helps with fine-tuning interrupt control and handling on that core:
在內核中每個核心的CPU接口有助於修正中斷的控制和處理:
12.2.2 Initialization
12.2.2初始化
Both the distributor and the CPU interfaces are disabled at reset.
經銷商和CPU接口在重置禁用。
The GIC must be initialized after reset before it can deliver interrupts to the core.
新加坡政府投資公司必須初始化復位後才能交付核心中斷。
In the distributor, software must configure the priority, target, security and enable individual interrupts.
軟件必須配置優先級經銷商,目標,安全,使個人的中斷。
The distributor block must subsequently be enabled through its control register.
經銷商塊隨後必須通過其控制寄存器。
For each CPU interface, software must program the priority mask and preemption settings.
爲每個CPU接口,軟件必須程序優先面具和搶佔設置。
Each CPU interface block itself must be enabled through its control register.
每個CPU接口塊本身必須啓用通過其控制寄存器。
This prepares the GIC to deliver interrupts to the core.
這個準備GIC將中斷。
Before interrupts are expected inthe core, software prepares the core to take interrupts by setting a valid interrupt vector in the vector table, and clearing interrupt masks bits in the CPSR.
中斷之前預計在覈心,核心軟件準備採取中斷矢量表中通過設置一個有效的中斷向量,並清除中斷CPSR面具碎片。
The entire interrupt mechanism in the system can be disabled by disabling the distributor block.
整個系統中的中斷機制可以通過禁用分銷商的塊被禁用。
Interrupt delivery to an individualcore can be disabled by disabling its CPU interface block, or by setting mask bits in CPSR of that core.
可以禁用中斷交付一個individualcore禁用其CPU接口塊,或通過設置掩碼位CPSR的核心。
Individual interrupts can also be disabled (or enabled) in the distributor.
個人也可以禁用中斷(或啓用)分銷商。
For an interrupt to reach the core, the individual interrupt, distributor and CPU interface must all be enabled, and the CPSR interrupt mask bits cleared.
一箇中斷到達核心,個人中斷,分銷商和CPU接口都必須被啓用,和CPSR中斷屏蔽位清除。
12.2.3 Interrupt handling
12.2.3中斷處理
When the core takes an interrupt, it jumps to the top-level interrupt vector obtained from the vector table and begins execution.
核心需要一箇中斷時,跳轉到中斷向量的向量頂級表並開始執行。
The top-level interrupt handler reads the Interrupt Acknowledge Registerfrom the CPU Interface block to obtain the interrupt ID.As well as returning the interrupt ID, the read causes the interrupt to be marked as active in the distributor.
頂級中斷處理程序讀取中斷承認Registerfrom CPU接口塊獲取中斷ID.As中斷返回ID,閱讀使中斷標記爲活躍的分銷商。
Once the interrupt ID is known (identifying the interrupt source), the top-level handler can now dispatch a device-specific handler to service the interrupt.
一旦中斷ID是已知的(確定中斷源),頂級處理器可以派遣一個特定於設備的處理程序服務中斷。
When the device-specific handler finishes execution, the top-level handler writes the same
特定於設備的處理程序執行完成時,高層處理程序寫相同的
interrupt ID to the End of Interrupt register in the CPU Interface block, indicating the end of
中斷ID的中斷寄存器在CPU接口,表示結束
interrupt processing.
中斷處理。
Apart from removing the active status, which will make the final interrupt status either Inactive, or Pending (if the state was Active and Pending), this will enable the CPU Interface to forward more pending interrupts to the core.
除了刪除活動狀態,這將使最終的中斷狀態不活躍,或等待(如果國家活躍和等待),這將使CPU接口轉發更多等待中斷的核心。
This concludes the processing of a single interrupt.
這就是一箇中斷的處理。
It is possible for there to be more than one interrupt waiting to be serviced on the same core, but the CPU Interface can signalonly one interrupt at a time.
有可能有多箇中斷等待服務相同的核心,但CPU接口可以signalonly中斷一次。
The top-level interrupt handler repeats the above sequence until it reads the special interrupt ID value 1023, indicating that there are no more interrupts pending at this core.
頂級中斷處理程序重複上述序列,直到1023年它讀取特殊中斷ID值,表明沒有中斷等待在這個核心。
This special interrupt ID is called the spurious interrupt ID. The spurious interrupt ID is a reserved value, and cannot be assigned to any device in the system.
這種特殊的中斷ID被稱爲僞中斷ID。僞中斷ID是一個保留價值,並且不能分配給系統中任何設備。
When the top-level handler has read the spurious interrupt ID it can complete its execution, and prepare the core to resume the task it was doing before taking the interrupt.
當頂級處理器讀過僞中斷ID可以完成其執行,並準備簡歷的核心任務是做之前中斷。