本文純屬個人筆記瞎粘貼性質。
HPET:
High Precision Event Timer
An HPET chip consists of a 64-bit up-counter (main counter) counting at a frequency of at least 10 MHz, and a set of (at least 3, up to 256) comparators. These comparators are 32- or 64-bit wide. The HPET is programmed via a memory mapped I/O window that
is discoverable via ACPI. The HPET circuit in modern PCs is integrated into the southbridge chip.
TSC:
Time Stamp Counter
The instruction RDTSC returns the TSC in EDX:EAX.
the TSC cannot be relied on to provide accurate results — unless great care is taken to correct the possible flaws: rate of
tick and whether all cores (processors) have identical values in their time-keeping registers.There is no promise that the timestamp counters of multiple
CPUs on a single motherboard will be synchronized.
這貨可能不是單調遞增，如果一個線程在多個核心上交替執行的話。它的tick頻率也會隨着CPU平率的改變而改變，而目前CPU爲了節能都會根據loading是否重而改變自身頻率。總之這貨非專業勿用。。
APIC:
Advanced Programmable Interrupt Controller
Interrupt requests can be controlled using two ways:
1. At device end - An Interrupt Enable bit in a control register determines whether device is allowed to generate an interrupt request.
2. At processor end - A priority structure and an interrupt mask in the PS determine whether a given interrupt request is accepted.
Local APICs
LAPICs manage all external interrupts for some specific processor in an SMP system. In addition, it is able to accept and generate inter-processor interrupts (IPIs) between LAPICs. LAPICs may support up to 224 usable interrupt vectors from an I/O APIC. Vectors
numbers 0 to 31, out of 0 to 255, are reserved for exception handling by x86 processors.
I/O APICs
I/O APICs contain a redirection table, which is used to route the interrupts it receives from peripheral buses to one or more local APICs.
待續。。。