1、minimum pulse width summary
Reports the results of minimum pulse width and minimum period checks.
A minimum pulse width check verifies that a clock high ("High") or low
("Low") pulse sustains long enough to qualify as a recognizable change
in the clock signal at a register clock pin. A failed minimum pulse
width check indicates that the register may not recognize the clock
transition. Each register in the design is reported twice per clock
for mininum pulse width checks: once for the high pulse and once for
the low pulse.
A minimum period check verifies that the clock period ("Period") is
large enough for the device to operate. Minimum period checks apply
to I/O edge rate limits for clock ports and minimum period
restrictions for RAM and DSP registers. Output clock ports (e.g.,
source synchronous clocks) require generated clocks in order to check
I/O edge rate limits for those those ports.
