實驗一 計算器
摘要:本DC綜合實驗設計了一個簡單的二進制計數器,由FSM(Finite State Machine)控制完成正向計數或者負向計數,並給出了設計源碼和綜合步驟及結果。
綜合工具:DC2005
1. 數據準備
(1)設置DC的工作環境,即啓動文件:在工作目錄下/home/ic401digital/kinglin/design/lab1中建立“.synopsys_dc.setup”文件,如下:
set search_path {/home/ic401digital/kinglin/design/lib}
set target_libray {tc6a.db}
set link_library {tc6a.db opcon.db}
set symbol_library {tc6a.sdb}
(2)編寫設計代碼,如下:
module counter (up_down, clk, counter_out);
input up_down, ckl;
output [1:0] counter_out;
reg [1:0] counter_out;
always @ (posedge clk)
begin
if (up_down)
counter_out <= counter_out + 1;
else
counter_out <= counter_out – 1;
end
endmodule
(3)約束腳本,如下:
analyze –format verilog -library DEFFAULT {/home/ic401digital/kinglin/design/lab1/src/counter.v}
elaborate counter –library DEFFAULT
current_design counter
link
set_operating_conditions slow_7_4.50
create_clock –period 50 –name clk [get_ports clk]
set_dont_touch_network [get_clocks clk]
set_input_delay 1 –clock clk [all_inputs]
set_drive 0 [all_inputs]
set_output_delay 1 –clock clk [all_outputs]
set_load 0.5
set_max_area 0
report_timg > /home/ic401digital/kinglin/design/lab1/rpt/timing.rpt
report_power > /home/ic401digital/kinglin/design/lab1/rpt/power.rpt
report_area > /home/ic401digital/kinglin/design/lab1/rpt/area.rpt
write –format db –hieararchy –output /home/ic401digital/kinglin/design/lab1/syn/counter.db
write –format verilog –hieararchy –output /home/ic401digital/kinglin/design/lab1/syn/counter.sv
write_sdf /home/ic401digital/kinglin/design/lab1/syn/counter.sdf
write_sdc /home/ic401digital/kinglin/design/lab1/syn/counter.sdc
2. 通過終端進入工作目錄/home/ic401digital/kinglin/design/lab1,鍵入:design_vision;啓動DC.
3. 執行上述腳本即可完成計數器的綜合。
4. 綜合的結果
(1)門級網表文件:加上庫文件,可進行門級仿真。
module counter( up_down, clk, counter_out );
output [1:0] counter_out;
input up_down, clk;
wire N3, N4, N5, N6, N7, n2;
fd1a2 / counter_out _reg[0] ( .D(N6), .CLK(Clock_In), .Q(counter_out [0]) );
fd1a2 / counter_out _reg[1] ( .D(N7), .CLK(Clock_In), .Q(counter_out [1]) );
ao4a2 U4 ( .A(N5), .B(n2), .C(up_down), .D(N3), .Y(N7) );
inv1a1 U6 ( .A(counter_out [0]), .Y(N4) );
ao4b0 U7 ( .C(N4), .D(n2), .B(up_down), .A(counter_out [0]), .Y(N6) );
inv1a1 U8 ( .A(up_down), .Y(n2) );
xor2a2 U9 ( .A(counter_out [1]), .B(counter_out [0]), .Y(N3) );
xor2a2 U10 ( .A(N4), .B(counter_out [1]), .Y(N5) );
endmodule
(2)標準單元延遲文件SDF:可用於時序驅動下的佈局佈線。
(3)SDC文件:包含了DC的時序、面積等約束信息。