1. Reading in db files is much faster than having to analyze/elaborate the design.
2. synthesis = translation + optimization + mapping
3. translation is performed by the analyze/elaborate command, whereas optimization/mapping is performed by the compile command.
4. analyze: (1)read the source code into the dc memory ;(2)perform the syntax and synthesis policy checks; (3) write the intermediate files to the directory specified as your library
5. elaborate: (1) read the intermediate files from your design library; (2) buid the design using the generic components (DC GTECH Library).
6. compile: (1)optimize the design; (2)map the design to real gates from your target library (technology library from the vendor); (3 ) produce a circuit that meets your constraints; (4) the unmapped design in the dc memory is overwriten by the new, mapped design.
7. constrain: a series of steps your perform to tell DC what your timing and area requirments. Typical constraints include clock period, signal arrival timesm maxium allowable area, load and drive characteristic, operating conditions etc.