本文將閱讀TMS320C6713的數據手冊（Datasheet）過程記錄下來。
因爲本次閱讀數據手冊的目的是獲取最小系統的硬件設計相關的信息，因此將會說明如何篩選數據手冊中的相關部分閱讀。
TMS320C6713的數據手冊可以在http://www.alldatasheet.com/搜索下載獲得，也可以到TI官網下載。
1. 確定閱讀目標
爲繪製TMS320C6713的最小系統，因此，主要關注核心的硬件，比如供電、復位、時鐘以及啓動方式配置等。如果不添加相關的外設，則數據手冊中有關外設的講解可以略過。
2. 閱讀數據手冊首頁的關於芯片功能的基本信息
數據手冊上的第一頁很重要，比如從上面很容易就可以看出6713爲浮點DSP，主頻、指令速度等。
還有啓動的配置方式，封裝方式，供電方式，這些是在設計最小系統時都需要考慮的問題。比如我們從中可以看出，6713分別需要3.3V和1.2給IO口和DSP內核供電，因此我們必需設計電源電路能同時產生1.2V和3.3V的穩定供電電壓。
3. 熟悉最小系統的構成
TMS320C6713最小系統由7部分組成，
熟悉了最小系統我們就知道電路設計過程中要完成哪些功能呢，在繼續閱讀數據手冊時也知道要關注哪些功能了。
我們要關注電源的設計，功能設置一般包括啓動方式配置，下載方式配置，存儲器訪問方式配置等等，關注復位的方法（高電平復位？低電平復位），關注需要哪幾種時鐘，是否需要外擴存儲器、存儲器的映射關係（如果要外擴存儲器需要知道映射關係）。JTAG電路一般比較固定，可以在網絡上查找近乎固定的電路模式，但不同芯片的JTAG電路略有不同，注意區分。DSP6713使用14腳的JTAG接口。
4. 快速閱覽數據手冊
如果這是第一次閱讀該數據手冊，強烈建議先不要直接大範圍地跳着閱讀，而應該“閱覽”，閱覽指快速的往下讀，覺得與最小系統設計無關的部分可以直接很快跳過。
閱讀時對芯片整體系統的描述最好仔細閱讀，比如下面的描寫6713處理器特性的表格和功能圖（對存在的外設要知道外設是幹嘛用的，但不用知道用法），其它相關的內容應該形成一個框架，需要知道大致的位置，需要時再詳細閱讀。
存儲器的映射圖
若外擴存儲器，外擴存儲器的地址至少從0x8000 0000（EMIF CE0）開始。
數據手冊接着就是各種詳細的關於外設的寄存器配置了，這些可以暫時不用去管，記住大概位置，快速翻過，用到的時候再詳細看，接着往下，看到“DEVICE CONFIGURATIONS”，設備配置，當然很重要了（與最小系統中的功能設置部分對應），我們要詳細地看看，如果可以還可以按照自己的方式做個筆記，首先有下面一段，
On the C6713 device, bootmode and certain device configurations/peripheral selections are determined at
device reset, while other device configurations/peripheral selections are software-configurable via the device
configurations register (DEVCFG) [address location 0x019C0200] after device reset.
爲什麼要有設備配置？因爲現在的芯片有很管腳具備複用功能（有多種功能），我們要按照自己的方式配置成自己需要的功能。
上面那段話的意思是說：啓動模式和設備配置/外設選擇在設備復位時決定了（暗指上電時就由硬件決定了），還有一些設備配置是由軟件寄存器（DEVCFG）配置的。很明顯，我們這裏更關注上電前硬件要做哪些配置。
哦，這手冊很總結地對要進行復位時要配置好的硬件部分進行了描述（H12的上拉，HD8大小端配置，HD[4:3]啓動模式，CLKMODE0時鐘選擇模式），我在自己的電路中選擇配置爲HD12=1上拉，HD8=1小端，HD[4:3]=10，CLKMODE0=1方波時鐘輸入。除了對芯片的模式進行配置外，還要對“外設選擇”進行配置（下圖），這裏配置HD14=0即不使能HPI。
接着往下看，“TERMINAL FUNCTIONS”，管腳功能，我們記住該位置（可以在pdf中添加書籤），暫不細看，在繪製芯片的原理圖封裝時主要參考該表格。
表格中描述了管腳信號名稱，管腳號，管腳類型（輸入/輸出/三態等），也對管腳功能做了描述。
接下來看到TMS320C6000系列的命名方法，作爲課外知識學習下，
接着，看到曙光——“文檔支持”，該部分給出了一些參考文檔，是繼續深入學習的最好參考資料，因此至少要記着有這麼些資料可供參考。
還有很多資源可以從TI的官網上獲得。
然後數據手冊中有一大塊是對各種外設寄存器的描述，可暫時跳過。
然後，也是這裏關注的重點，電源供電：（1）電源供電順序是DSP核要比IO口先上電，斷電順序剛好相反，數據手冊上給出了相應的電源供電電路的方案，
數據手冊中還對供電去耦的相關內容進行了描述：
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible
close to the DSP. Assuming 0603 caps, the user should be able to fit a total of 60 caps — 30 for the core supply
and 30 for the I/O supply. These caps need to be close (no more than 1.25 cm maximum distance) to the DSP
to be effective. Physically smaller caps are better, such as 0402, but the size needs to be evaluated from a
yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling capacitors,
therefore physically smaller capacitors should be used while maintaining the largest available capacitance
value. As with the selection of any component, verification of capacitor availability over the product’s production
lifetime needs to be considered.
接着還對JTAG的接口、啓動模式（Bootmode）和復位相關的內容進行了描述。
（1）JTAG的接口
The TMS320C6713 DSP requires that both TRSTand RESETresets be asserted upon power up to be properly
initialized. While RESETinitializes the DSP core, TRSTinitializes the DSP’s emulation logic. Both resets are
required for proper operation.
Note: TRSTis synchronous and must be clocked by TCLK; otherwise, BSCAN may not respond as expected
after TRSTis asserted.
While both TRSTand RESETneed to be asserted upon power up, only RESETneeds to be released for the
DSP to boot properly. TRSTmay be asserted indefinitely for normal operation, keeping the JTAG port interface
and DSP’s emulation logic in the reset state. TRSTonly needs to be released when it is necessary to use a JTAG
controller to debug the DSP or exercise the DSP’s boundary scan functionality.
The TMS320C6713 DSP includes an internal pulldown (IPD) on the TRSTpin to ensure that TRSTwill always
be asserted upon power up and the DSP’s internal emulation logic will always be properly initialized when this
pin is not routed out. JTAG controllers from Texas Instruments actively drive TRSThigh. However, some
third-party JTAG controllers may not drive TRSThigh but expect the use of an external pullup resistor on TRST.
When using this type of JTAG controller, assert TRSTto initialize the DSP after powerup and externally drive
TRSThigh before attempting any emulation or boundary scan operations.
Following the release of RESET, the low-to-high transition of TRSTmust be “seen” to latch the state of EMU1
and EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Emulation mode. For
more detailed information, see the terminal functions section of this data sheet. Note: The DESIGN−WARNING
section of the TMS320C6713 BSDL file contains information and constraints regarding proper device operation
while in Boundary Scan Mode. For more detailed information on the C6713 JTAG emulation, see the
TMS320C6000 DSP Designing for JTAG Emulation Reference Guide(literature number SPRU641).
（2）啓動模式
The C6713 has three types of boot modes:
Host boot
If host boot is selected, upon release of internal reset, the CPU is internally “stalled” while the remainder of
the device is released. During this period, an external host can initialize the CPU’s memory space as
necessary through the host interface, including internal configuration registers, such as those that control
the EMIF or other peripherals. Once the host is finished with all necessary initialization, it must set the
DSPINT bit in the HPIC register to complete the boot process. This transition causes the boot configuration
logic to bring the CPU out of the “stalled” state. The CPU then begins execution from address 0. The DSPINT
condition is not latched by the CPU, because it occurs while the CPU is still internally “stalled”. Also, DSPINT
brings the CPU out of the “stalled” state only if the host boot process is selected. All memory may be written
to and read by the host. This allows for the host to verify what it sends to the DSP if required. After the CPU is
out of the “stalled” state , the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received.
Emulation boot
Emulation boot mode is a variation of host boot. In this mode, it is not necessary for a host to load code or to
set DSPINT to release the CPU from the “stalled” state. Instead, the emulator will set DSPINT if it has not
been previously set so that the CPU can begin executing code from address 0. Prior to beginning execution,
the emulator sets a breakpoint at address 0. This prevents the execution of invalid code by halting the CPU
prior to executing the first instruction. Emulation boot is a good tool in the debug phase of development.
EMIF boot (using default ROM timings)
Upon the release of internal reset, the 1K-Byte ROM code located in the beginning of CE1is copied to
address 0 by the EDMA using the default ROM timings, while the CPU is internally “stalled”. The data should
be stored in the endian format that the system is using. The boot process also lets you choose the width of
the ROM. In this case, the EMIF automatically assembles consecutive 8-bit bytes or 16-bit half-words to
form the 32-bit instruction words to be copied. The transfer is automatically done by the EDMA as a
single-frame block transfer from the ROM to address 0. After completion of the block transfer, the CPU is
released from the “stalled” state and start running from address 0.
（3）復位
A hardware reset (RESET) is required to place the DSP into a known good state out of power−up.The RESET
signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core and I/O voltages
have reached their proper operating conditions. As a best practice, reset should be held low during power−up.
Prior to deasserting RESET(low−to−high transition), the core and I/O voltages should be at their proper
operating conditions and CLKIN should also be running at the correct frequency.
再接着數據手冊的後面就是一些相關的時序，在編程時尤爲關鍵，但不是現在考慮的問題；最後就是機械封裝結構了，PCB封裝的繪製主要參考數據手冊結尾處的機械封裝描述。
5. 結尾
到此，我們已經完整的閱覽了遍TMS320C6713的數據手冊了。有人覺得閱讀數據手冊很枯燥，但有目的有重點地去閱讀，自我覺得閱讀數據手冊是瞭解一個芯片最快速有效的方法。在閱讀時注意：
（1）確定閱讀目標
（2）確定關注框架/內容：可以繪製思維導圖（推薦XMind軟件）幫助閱讀
（3）第一次閱讀要“閱覽”，並對重點但一時無法記憶的內容使用pdf書籤標記，其它次要內容知道大概位置就OK了，以後閱讀直接跳轉到需要了解的位置閱讀即可。
（4）"好記性不如爛筆頭“，數據手冊就是一本講解芯片的書，閱讀時要時刻注意總結記筆記。
原則上，一份100多頁的數據手冊在4個小時的時間內完全可以閱覽完，若4小時內沒有閱覽完畢，說明太過關注細節了，否則說明可能漏掉了重要的東西。