本文內容參考SATA3.3協議第15章節
15 Error Handling
15.1 Architecture
15.2 Phy error handling overview
There are three primary categories of error that the Phy layer detects internally:
a) no device present; // 對應SStatus register中DET值爲0000b
b) OOB signaling sequence failure; and // 對應SStatus register中DET值爲0001b
c) Phy internal error (loss of synchronization of communications link) // 對應SError register中ERR域中bit[E]表示爲phy internal error
前2個錯誤都是存儲在SStatus register裏，第三個錯誤存儲在SStatus register和SError register裏。
協議14.2.2中可以查看SStatus register
協議14.2.3中可以查看SError register
ERR域各bit詳細解釋見協議手冊
15.3 Link layer error handling overview
There are two primary categories of errors that the Link layer detects internally are:
a) invalid state transitions; and
b) data integrity errors.
Invalid state transition errors may arise from a number of sources and the Link layer responses to
many such error conditions as defined in clause 9. Data integrity errors generally arise from
noise in the physical interconnect.
第一個錯誤如果發生在frame傳輸給Phy的過程中，則在傳輸完SOF後，再傳輸個R_ERR；如果錯誤不是發生在frame傳輸過程中，則Link直接切換爲idle狀態，等待下一次操作。
15.4 Transport layer error handling
In addition to the error information passed to it by the Link layer, the Transport layer internally
detects the following categories of errors:
a) internal errors;
b) frame errors;
c) protocol errors; and
d) state errors.
傳輸層都會通知鏈路層所檢測到的error(SStatus and SError registers裏反映)，鏈路層再通過每次frame傳輸完成後的R_ERR/R_OK來報告錯誤(不過R_ERR相較於D2B FIS不能指出錯誤的原因)。
15.5 Application layer error handling
There are three overall error detection mechanisms that software identifies and responds to
Serial ATA errors:
a) bad status in the Command Block Status register;
b) bad status in the SError register; and
c) command failed to complete (i.e., timeout).