2 Comparator Block
The comparator module described in this reference guide is a true analog voltage comparator in the VDDA domain. The analog portion of the block include the comparator, its inputs and outputs, and the internal DAC reference. The digital circuits, referred to as the wrapper in this document, include the DAC controls, interface to other on-chip logic, output qualification block, and the control signals.
2.比較器模塊
在這個參考指南中所描述的比較器模塊是VDDA域中一個真正的模擬電壓比較器。模擬塊的一部分包含比較器，輸入和輸出，以及內部的DAC參考基準。數字電路在本文檔當中被稱爲程序輪詢，包括DAC控制，其他片上邏輯的接口，輸出限定單元和控制信號。
2.1 Features
The comparator block (see Figure 39) can accommodate two external analog inputs or one external analog input using the internal DAC reference for the other input. The output of the comparator can be passed asynchronously or qualified and synchronized to the system clock period. The comparator output is routed to both the ePWM Trip Zone modules, as well as the GPIO output multiplexer.
2.1 特性
比較器模塊（見圖39）可以提供兩個外部模擬輸入或者一個外部模擬輸入，其中另一個輸入使用內部的DAC參考基準。比較器的輸出異步傳輸，或者被限定成與系統時鐘週期同步。比較器的輸出被路由到ePWM TZ
模塊，也可以路由到GPIO輸出多路複用器。
2.2 Comparator Function
The comparator in each comparator block is an analog comparator module, and as such its output is asynchronous to the system clock. The truth table for the comparator is shown in Table 24.
2.2比較器功能
每一個比較器模塊中的比較器都是一個模擬比較器模塊，就其本身而言，其輸出與系統時鐘是異步的。比較器的真值表如表24所示。
There is no definition for the condition Voltage A = Voltage B since there is hysteresis in the response of the comparator output. Refer to the device datasheet for the value of this hysteresis. This also limits the sensitivity of the comparator output to noise on the input voltages. The output state of the comparator, after qualification, is reflected by the COMPSTS bit in the COMPSTS register. Since this bit is part of the wrapper, clocks must be enabled to the comparator block for the COMPSTS bit to actively show the comparator state.
上面沒有對Voltage A = Voltage B的條件進行定義，因爲比較器的輸出響應有滯後。滯後的值請參閱器件的數據手冊。比較器輸出靈敏度將受輸入電壓上的噪聲限值。經過限定後，比較器輸出的狀態受COMPSTS寄存器中COMPSTS位的影響。因爲這個位是輪詢程序的一部分，爲了COMPSTS位主動的顯示比較器的狀態，所以比較器模塊的時鐘必須使能。
Default state 缺省狀態
Round—robin 循環的
Raw 原始的
