2-1 Verilog 3-8 譯碼器

使用工：Xilinx ISE 14.7

在這裏涉及到了Verilog的條件語句對真值表進行翻譯，因爲有8種情況，所以選擇case語句，代碼如下：

module code(
	input [2:0] in,
	output reg [7:0] led
    );

always @ (*)
	case(in)
		3'b000: led = 8'b00000001;
		3'b001: led = 8'b00000010;
		3'b010: led = 8'b00000100;
		3'b011: led = 8'b00001000;
		3'b100: led = 8'b00010000;
		3'b101: led = 8'b00100000;
		3'b110: led = 8'b01000000;
		3'b111: led = 8'b10000000;
	endcase

endmodule

注意：由於使用always控制時序觸發，在always裏要使用reg而不是使用前文中的wire，wire適用與組合邏輯，用assign賦值

小建議：這是剛學時所寫的程序，語法不規範，最好在always下加個begin——end把case的內容囊括起來

測試文件：

initial begin
		// Initialize Inputs
		in = 0;
		#100;
		
		in = 1;
		#100;
		
		in = 2;
		#100;
		
		in = 3;
		#100;
		
		in = 4;
		#100;
		
		in = 5;
		#100;
		
		in = 6;
		#100;
		
		in = 7;
		#100;
		//end
		// Wait 100 ns for global reset to finish	    
		// Add stimulus here
	end

仿真結果：