使用工具: Xilinx ISE 14.7
挺簡單的不說什麼,直接貼代碼
源文件代碼:
module code(
input wire a,
input wire b,
output wire [5:0] z
);
assign z[0] = ~(a^b);
assign z[1] = a^b;
assign z[2] = ~(a|b);
assign z[3] = a|b;
assign z[4] = ~(a&b);
assign z[5] = a&b;
endmodule
測試文件代碼:module test1;
// Inputs
reg a;
reg b;
// Outputs
wire [5:0] z;
// Instantiate the Unit Under Test (UUT)
code uut (
.a(a),
.b(b),
.z(z)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
// Wait 100 ns for global reset to finish
#100;
a = 1;
b = 0;
#100;
a = 0;
b = 1;
#100;
a = 1;
b = 1;
#100;
// Add stimulus here
end
endmodule
仿真結果: