GD重新設置主頻的方法

SystemSelectPLL();
SystemCoreClockUpdate ();  //更新SystemCoreClock

vPortSetupTimerInterrupt();  // 更新Systick控制器的值

#if 0 // 48MHz
void SystemSelectPLL(void)
{
    uint32_t timeout = 0U;
    uint32_t stab_flag = 0U;

    if (RCU_CTL & RCU_CTL_HXTALEN) return;
    /* enable HXTAL */
    RCU_CTL |= RCU_CTL_HXTALEN;

    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
    do{
        timeout++;
        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));

    timeout = 0;
    /* if fail */
    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB))
    {
//        GTK_LOG_ERR(GTK_DBG_DRV_RTC, "RTC error %s", __func__);
        while(1)
        {
            timeout++;
            if (timeout > HXTAL_STARTUP_TIMEOUT)
            {
//                GTK_LOG_ASSERT(GTK_DBG_DRV_RTC, "RTC error %d", __LINE__);
//                GTK_ASSERT(0);
            }
            timeout = 0;
        }
    }

    RCU_APB1EN |= RCU_APB1EN_PMUEN; //10.12
    PMU_CTL |= PMU_CTL_LDOVS; //10.12

    /* enable PLL */
    RCU_CTL |= RCU_CTL_PLLEN;

    /* wait until PLL is stable */
    while(0U == (RCU_CTL & RCU_CTL_PLLSTB))
    {
        timeout++;
        if (timeout > HXTAL_STARTUP_TIMEOUT)
        {
//            GTK_LOG_ASSERT(GTK_DBG_DRV_RTC, "RTC error %d", __LINE__);
//            GTK_ASSERT(0);
        }
        timeout = 0;
    }

    /* enable the high-drive to extend the clock frequency to 48 MHz */
    PMU_CTL |= PMU_CTL_HDEN;
    while(0U == (PMU_CS & PMU_CS_HDRF)){
        timeout++;
        if (timeout > HXTAL_STARTUP_TIMEOUT)
        {
//            GTK_LOG_ASSERT(GTK_DBG_DRV_RTC, "RTC error %d", __LINE__);
//            GTK_ASSERT(0);
        }
        timeout = 0;
    }

    /* select the high-drive mode */
    PMU_CTL |= PMU_CTL_HDS;
    while(0U == (PMU_CS & PMU_CS_HDSRF)){
        timeout++;
        if (timeout > HXTAL_STARTUP_TIMEOUT)
        {
//            GTK_LOG_ASSERT(GTK_DBG_DRV_RTC, "RTC error %d", __LINE__);
//            GTK_ASSERT(0);
        }
        timeout = 0;
    }

    /* select PLL as system clock */
    RCU_CFG0 &= ~RCU_CFG0_SCS;
    RCU_CFG0 |= RCU_CKSYSSRC_PLL;

    /* wait until PLL is selected as system clock */
    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
        timeout++;
        if (timeout > HXTAL_STARTUP_TIMEOUT)
        {
//            GTK_LOG_ASSERT(GTK_DBG_DRV_RTC, "RTC error %d", __LINE__);
//            GTK_ASSERT(0);
        }
        timeout = 0;
    }
}
#endif

#if 1  // 16MHz
//static void system_clock_16m_hxtal(void)
void SystemSelectPLL(void)
{
    uint32_t timeout = 0U;
    uint32_t stab_flag = 0U;

    /* enable HXTAL */
    RCU_CTL |= RCU_CTL_HXTALEN;

    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
    do{
        timeout++;
        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));

    /* if fail */
    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
    while(1){
            }
    }

    RCU_APB1EN |= RCU_APB1EN_PMUEN;
    PMU_CTL |= PMU_CTL_LDOVS;

    /* HXTAL is stable */
    /* AHB = SYSCLK */
    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
    /* APB2 = AHB/1 */
    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
    /* APB1 = AHB/2 */
    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;

    /* select HXTAL/2 as clock source */
    RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0);
    RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0);

    /* CK_PLL = (CK_HXTAL/2) * 4 = 16 MHz */
    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
    RCU_CFG0 |= RCU_PLL_MUL4;

    /* enable PLL */
    RCU_CTL |= RCU_CTL_PLLEN;

    /* wait until PLL is stable */
    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
   }

    /* enable the high-drive to extend the clock frequency to 16 MHz */
    PMU_CTL |= PMU_CTL_HDEN;
    while(0U == (PMU_CS & PMU_CS_HDRF)){
    }

    /* select the high-drive mode */
    PMU_CTL |= PMU_CTL_HDS;
    while(0U == (PMU_CS & PMU_CS_HDSRF)){
    }

    /* select PLL as system clock */
    RCU_CFG0 &= ~RCU_CFG0_SCS;
    RCU_CFG0 |= RCU_CKSYSSRC_PLL;

    /* wait until PLL is selected as system clock */
    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
   }
}
#endif

 

 

 

只是選擇PLL設置，不是設置主頻