31--阻塞與非阻塞賦值移位寄存器的幾種仿真

`timescale 1ns/1ns 
 module tb_block(); 
 wire Q0,Q1,Q2,Q3; 
 reg clk,din; 

 block1 u1(.clk(clk),.din(din),.Q0(Q0),.Q1(Q1),.Q2(Q2),.Q3(Q3));

initial begin
clk<=1'b0;
din<=1'b0;
#50 din<=1'b1;
end
always #5 clk<=~clk;
endmodule


 module block1(Q0,Q1,Q2,Q3,din,clk); 

 output Q0,Q1,Q2,Q3; 

 input clk,din; 


     reg Q0,Q1,Q2,Q3; 

     always @(posedge clk) 

           begin 

           Q3=Q2;                //注意賦值語句的順序 

           Q2=Q1; 

           Q1=Q0; 

           Q0=din; 

           end 

     endmodule 

     module block2(Q0,Q1,Q2,Q3,din,clk); 

     output Q0,Q1,Q2,Q3; 

     input clk,din; 

     reg Q0,Q1,Q2,Q3; 

     always @(posedge clk) 

           begin 

           Q3=Q2; 

           Q1=Q0;               

           Q2=Q1; 

           Q0=din; 

           end 

     endmodule 
     
`timescale 1ns/1ns 
 module tb_block(); 
 wire Q0,Q1,Q2,Q3; 
 reg clk,din; 

 block2 u1(.clk(clk),.din(din),.Q0(Q0),.Q1(Q1),.Q2(Q2),.Q3(Q3));

initial begin
clk<=1'b0;
din<=1'b0;
#50 din<=1'b1;
end
always #5 clk<=~clk;
endmodule

     module block3(Q0,Q1,Q2,Q3,din,clk); 

     output Q0,Q1,Q2,Q3; 

     input clk,din; 

     reg Q0,Q1,Q2,Q3; 

     always @(posedge clk) 

          begin 

          Q0=din;                //4條賦值語句的順序與例 10.11完全顛倒 

          Q1=Q0; 

          Q2=Q1; 

          Q3=Q2; 

          end 

     endmodule 

`timescale 1ns/1ns 
 module tb_block(); 
 wire Q0,Q1,Q2,Q3; 
 reg clk,din; 

 block3 u1(.clk(clk),.din(din),.Q0(Q0),.Q1(Q1),.Q2(Q2),.Q3(Q3));

initial begin
clk<=1'b0;
din<=1'b0;
#50 din<=1'b1;
end
always #5 clk<=~clk;
endmodule

 module block4(Q0,Q1,Q2,Q3,din,clk); 
 

 output Q0,Q1,Q2,Q3; 

 input clk,din; 

 reg Q0,Q1,Q2,Q3; 

 always @(posedge clk) 

     begin 

      Q3<=Q2; 

      Q1<=Q0; 

      Q2<=Q1; 

      Q0<=din; 

      end 

endmodule 

`timescale 1ns/1ns 
 module tb_block(); 
 wire Q0,Q1,Q2,Q3; 
 reg clk,din; 

 block4 u1(.clk(clk),.din(din),.Q0(Q0),.Q1(Q1),.Q2(Q2),.Q3(Q3));

initial begin
clk<=1'b0;
din<=1'b0;
#50 din<=1'b1;
end
always #5 clk<=~clk;
endmodule