簡介
在 xtensa ISA(指令集架構) 參考文檔中, 描述了:
將執行重定向到一個常規異常向量 (userExceptionVector、kernelExceptionVector 或 doubleExceptionVector) 的異常之後, EXCCAUSE 寄存器將包含一個值, 該值指定上次異常的原因. CPU 重置後, EXCCAUSE 將處於未定義狀態.
下圖爲 EXCCAUSE 寄存器的比特位數顯示.
異常原因 (Exception Causes)
| EXCCAUSE Code ( EXCCAUSE 寄存器最後 6-bit 值) |
Cause Name | Cause Description [Required Option] | EXCVADDR Loaded |
|---|---|---|---|
| 0 | IllegalInstructionCause | Illegal instruction [Exception Option] | No |
| 1 | SyscallCause | SYSCALL instruction [Exception Option] | No |
| 2 | InstructionFetchErrorCause | Processor internal physical address or data error during instruction fetch [Exception Option] | Yes |
| 3 | LoadStoreErrorCause | Processor internal physical address or data error during load or store [Exception Option] | Yes |
| 4 | Level1InterruptCause | Level-1 interrupt as indicated by set level-1 bits in the INTERRUPT register [ Interrupt Option ] | No |
| 5 | AllocaCause | MOVSP instruction, if caller’s registers are not in the register file [ Windowed Register Option] | No |
| 6 | IntegerDivideByZeroCause | QUOS, QUOU, REMS, or REMU divisor operand is zero [ 32-bit Integer Divide Option] | No |
| 7 | / | Reserved for Tensilica | / |
| 8 | PrivilegedCause | Attempt to execute a privileged operation when CRING ≠ 0 [MMU Option] | No |
| 9 | LoadStoreAlignmentCause | Load or store to an unaligned address [Unaligned Exception Option] | Yes |
| 10…11 | / | Reserved for Tensilica | / |
| 12 | InstrPIFDataErrorCause | PIF data error during instruction fetch [Processor Interface Option] | Yes |
| 13 | LoadStorePIFDataErrorCause | Synchronous PIF data error during LoadStore access [Processor Interface Option] | Yes |
| 14 | InstrPIFAddrErrorCause | PIF address error during instruction fetch [Processor Interface Option] | Yes |
| 15 | LoadStorePIFAddrErrorCause | Synchronous PIF address error during LoadStore access [Processor Interface Option] | Yes |
| 16 | InstTLBMissCause | Error during Instruction TLB refill [MMU Option] | Yes |
| 17 | InstTLBMultiHitCause | Multiple instruction TLB entries matched [MMU Option] | Yes |
| 18 | InstFetchPrivilegeCause | An instruction fetch referenced a virtual address at a ring level less than CRING [MMU Option] | Yes |
| 19 | / | Reserved for Tensilica | / |
| 20 | InstFetchProhibitedCause | An instruction fetch referenced a page mapped with an attribute that does not permit instruction fetch [Region Protection Option or MMU Option] | Yes |
| 21…23 | / | Reserved for Tensilica | / |
| 24 | LoadStoreTLBMissCause | Error during TLB refill for a load or store [MMU Option] | Yes |
| 25 | LoadStoreTLBMultiHitCause | Multiple TLB entries matched for a load or store [MMU Option] | Yes |
| 26 | LoadStorePrivilegeCause | A load or store referenced a virtual address at a ring level less than CRING [MMU Option] | Yes |
| 27 | / | Reserved for Tensilica | / |
| 28 | LoadProhibitedCause | A load referenced a page mapped with an attribute that does not permit loads [Region Protection Option or MMU Option] | Yes |
| 29 | StoreProhibitedCause | A store referenced a page mapped with an attribute that does not permit stores [Region Protection Option or MMU Option] | Yes |
| 30…31 | / | Reserved for Tensilica | / |
| 32…39 | CoprocessornDisabled | Coprocessor n instruction when cpn disabled. n varies 0…7 as the cause varies 32…39 [Coprocessor Option] | No |
| 40…63 | / | Reserved for Tensilica | / |