轉貼：http://hi.baidu.com/shmcn/blog/item/b849d4a28832d8adcaefd0a1.html
Semihosting，顧名思義，就是"半主控"，意思就是說，運行在target board上的程序利用主機上的facilities的一種程序調試方式，主要是debug目標板時，利用主機的輸入輸出設備，例如在AxD的console上打印相應的調試信息或者用主機的鍵盤輸入相應字符作爲target上的程序的輸入。
C/C++ code默認是可以使用console的，例如，如果只包含C/C++的程序採用ARMulater模擬，就可以直接使用console作爲程序的輸出設備；如果程序包含有彙編代碼，要使用主機設備的話，必須採用semihosting SWI方式。Semihosing SWI(以下簡稱SHS)，必須有相應的debug agent的支持，才能截獲SHS，並向software debugger(AxD)請求相應的服務，如打印字符或者接受字符輸入，這樣的agents包括:
1)ARMulater
2)debug monitor（Angel）
3)MultiICE
由於調試裸板或者沒有Angel可以供目標板使用的時候，主要還是要藉助仿真器進行調試，所以第三種方式最爲常用，下面主要就這種方式進行介紹。當然，UART也是一種最常用的調試接口，但是，使用Semihosting，可以獨立地調試各個硬件模塊的邏輯功能，確保各段代碼正確後再進行集成，相應地省去了每次都要配置UART和另開一個hyperterminal觀察調試信息。所以，我在開發的時候傾向於使用semihosting來調試相關的代碼，這些代碼使用C或者C++編寫，也就是說和硬件配置關係不大。
=================================Below from ADS help===============================
Multi-ICE
When using Multi-ICE in default configuration, semihosting is implemented as follows:
1. On ARM7 processors:
a) A breakpoint is set on the SWI vector.
b) When this breakpoint is hit, Multi-ICE examines the SWI number.
c) If the SWI is recognized as a semihosting SWI, Multi-ICE emulates it and transparently restarts execution of the application.
If the SWI is not recognized as a semihosting SWI, Multi-ICE halts the processor and reports an error.
2. On other processors:
a) Vector-catch logic traps SWIs.
b) If the SWI is recognized as a semihosting SWI, Multi-ICE emulates it and transparently restarts execution of the application.
If the SWI is not recognized as a semihosting SWI, Multi-ICE halts the processor and reports an error.
This semihosting mechanism can be disabled or changed by the following debugger internal variables:
$semihosting_enabled
Set this variable to 0 to disable semihosting. If you are debugging an application running from ROM, this allows you to use an additional watchpoint unit.
Set this variable to 1 to enable semihosting. This is the default.
Set this variable to 2 to enable Debug Communications Channel semihosting.
The S bit in $vector_catch has no effect unless semihosting is disabled.
$semihosting_vector
This variable controls the location of the breakpoint set by Multi-ICE to detect a semihosted SWI. It is set to the SWI entry in the exception vector table (0x8) by default.
If your application requires semihosting as well as having its own SWI handler, set $semihosting_vector to an address in your SWI handler. This address must point to an instruction that is only executed if your SWI handler has identified a call to a semihosting SWI. All registers must already have been restored to whatever values they had on entry to your SWI handler.
Multi-ICE handles the semihosted SWI and then examines the contents of lr and returns to the instruction following the SWI instruction in your code.
Regardless of the value of $vector_catch, all exceptions and interrupts are trapped and reported as an error condition.
For details of how to modify debugger internal variables, see the appropriate debugger documentation.