VBAR_EL1, Vector Base Address Register (EL1)
Holds the vector base address for any exception that is taken to EL1.
VBAR_EL2, Vector Base Address Register (EL2)
Holds the vector base address for any exception that is taken to EL2.
VBAR_EL3, Vector Base Address Register (EL3)
Holds the vector base address for any exception that is taken to EL3.
ARMv8 針對異常進入定義的基址寄存器。即存放異常向量表的基地址，一般在系統啓動的早期進行設置。
Disassembly of section .text:
00000000f8000000 <bl2_entrypoint>:
f8000000: aa0003f4 mov x20, x0
f8000004: aa0103f5 mov x21, x1
f8000008: aa0203f6 mov x22, x2
f800000c: aa0303f7 mov x23, x3
f8000010: 10043f80 adr x0, f8008800 <SynchronousExceptionSP0> 獲取異常向量基地址
f8000014: d51ec000 msr vbar_el3, x0 設置基地址到EL3,此時處於EL3級別
f8000018: d5033fdf isb
f800001c: 58000421 ldr x1, f80000a0 <bl2_entrypoint+0xa0> 把後面地址f80000a0存放到X1
f8000020: f9400020 ldr x0, [x1]， 這裏把X1裏面存放的內容作爲地址，獲取此地址裏面內容
f8000024: 92400c00 and x0, x0, #0xf ; 檢查低4位是否有內容，
f8000028: f100001f cmp x0, #0x0； 比較是否爲非0指
f800002c: 5403e361 b.ne f8007c98 <bl2_sysdump> // b.any 非0則跳轉到bl2_sysdump處理
f8000030: 94000022 bl f80000b8 <drop_to_el1>//處理跳轉到EL1
f8000034: 10047e60 adr x0, f8009000 <SynchronousExceptionSP0>;繼續把el1的異常向量基地址設置
f8000038: d518c000 msr vbar_el1, x0 到vbar_el1中
f800003c: d5033fdf isb 再進行指令同步
f8000040: d50344ff msr daifclr, #0x4 把 SError interrupt給掩碼了。
f8000044: d2820141 mov x1, #0x100a // #4106
f8000048: d5381000 mrs x0, sctlr_el1
f800004c: aa010000 orr x0, x0, x1，這裏執行邏輯或指令，就是把上面立即數4106即(0B1 0000 0000 1010)
f8000050: d5181000 msr sctlr_el1, x0; 這裏是配置SCTLR_EL1寄存器
f8000054: d5033fdf isb 再次執行指令同步
f8000058: 10067d40 adr x0, f800d000 <__RODATA_END__>獲取地址，即存放數據的數據段基地址
f800005c: 100b7d21 adr x1, f8017000 <__BL2_END__> 存放數據的結束地址
f8000060: cb000021 sub x1, x1, x0 ；獲取這個數據段長度
f8000064: 94001f70 bl f8007e24 <inv_dcache_range> ，這個是調用dcache 無效，即
f8000068: 58000200 ldr x0, f80000a8 <bl2_entrypoint+0xa8> 裝載地址，即把f80000a8 放入X0
f800006c: 58000221 ldr x1, f80000b0 <bl2_entrypoint+0xb0> 把f80000b0 放入x1
f8000070: 94001f7c bl f8007e60 <zeromem> 此函數針對x0和x1之間的存儲空間進行清零處理
f8000074: 94001f01 bl f8007c78 <plat_set_my_stack> 設置棧
f8000078: aa1403e0 mov x0, x20 恢復x20 - x23 到 x0-x3
f800007c: aa1503e1 mov x1, x21
f8000080: aa1603e2 mov x2, x22
f8000084: aa1703e3 mov x3, x23
f8000088: 94001bbc bl f8006f78 <bl2_early_platform_setup2> 跳轉到此處運行平臺相關處理
f800008c: 94000860 bl f800220c <bl2_plat_arch_setup> 體希結構相關初始化
f8000090: 940019f4 bl f8006860 <bl2_main>調用bl2的main處理函數
f8000094: 94001fc8 bl f8007fb4 <plat_panic_handler>
f8000098: d503201f nop
f800009c: 00000000 .inst 0x00000000 ; undefined
f80000a0: fa722180 .word 0xfa722180
f80000a4: 00000000 .word 0x00000000
f80000a8: f800e200 .word 0xf800e200 起始地址
f80000ac: 00000000 .word 0x00000000
f80000b0: 00003e50 .word 0x00003e50 長度
f80000b4: 00000000 .word 0x00000000
即數4106即(0B1 0000 0000 1010)
SCTLR_EL1, System Control Register (EL1)
Provides top level control of the system, including its memory system, at EL1 and EL0.
I, bit [12]
Instruction access Cacheability control, for accesses at EL0 and EL1:
0b0 All instruction access to Normal memory from EL0 and EL1 are Non-cacheable for all levels of instruction and unified cache.If the value of SCTLR_EL1.M is 0, instruction accesses from stage 1 of the EL1&0 translation regime are to Normal, Outer Shareable, Inner Non-cacheable, Outer Non-cacheable memory.
0b1 This control has no effect on the Cacheability of instruction access to Normal memory from EL0 and EL1.If the value of SCTLR_EL1.M is 0, instruction accesses from stage 1 of the EL1&0 translation regime are to Normal, Outer Shareable, Inner Write-Through, Outer Write-Through memory.
也就是說，上面操作開啓了I cache，即指令cache開啓。
SA, bit [3] 棧指針對齊檢查
SP Alignment check enable. When set to 1, if a load or store instruction executed at EL1 uses the
SP as the base address and the SP is not aligned to a 16-byte boundary, then a SP alignment fault
exception is generated. For more information, see SP alignment checking on page D1-2164.
When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit
has no effect on the PE.
In a system where the PE resets into EL1, this field resets to an architecturally UNKNOWN value.
C, bit [2] 數據cache關閉
Cacheability control, for data accesses.
0b0 All data access to Normal memory from EL0 and EL1, and all Normal memory accesses
to the EL1&0 stage 1 translation tables, are Non-cacheable for all levels of data and
unified cache.
0b1 This control has no effect on the Cacheability of:
• Data access to Normal memory from EL0 and EL1.
• Normal memory accesses to the EL1&0 stage 1 translation tables.
A, bit [1]
Alignment check enable. This is the enable bit for Alignment fault checking at EL1 and EL0.
0b0 Alignment fault checking disabled when executing at EL1 or EL0.
Instructions that load or store one or more registers, other than load/store exclusive and
load-acquire/store-release, do not check that the address being accessed is aligned to the
size of the data element(s) being accessed.
0b1 Alignment fault checking enabled when executing at EL1 or EL0.
All instructions that load or store one or more registers have an alignment check that the
address being accessed is aligned to the size of the data element(s) being accessed. If
this check fails it causes an Alignment fault, which is taken as a Data Abort exception.
M, bit [0] MMU關閉
MMU enable for EL1 and EL0 stage 1 address translation. Possible values of this bit are:
0b0 EL1 and EL0 stage 1 address translation disabled.
See the SCTLR_EL1.I field for the behavior of instruction accesses to Normal memory.
0b1 EL1 and EL0 stage 1 address translation enabled.