1, Dynamic latch comparator (slicer), rather than the traditional continuous time comparator, uses the "metastability" instead of "gain" or "bandwidth" to characterize the circuit design. [1]
2, To simulate the metastability, apply a small voltage (~10uV) to the slicer input, then toggle the clk to let the slicer sense. Then the output voltage waveform is monitored and the time for the waveform to change from latching node Vx=V1=1x to Vx=V2=2.718x(the constant 'e') is measured. (Vx=1x, e.g., Vx=10uV as an arbitrary small voltage, any small voltage is OK)
3, The time from Vx=1x to Vx=2.718x is labeled as tm. tm is a method to characterize the regeneration time constant of the slicer.
From the time constant, the error probability (bit error rate) of the slicer can be figured out by following formula:
Perror = (2 * VL) * exp(-T / tm) / ( AUL * Q) ["Comparator Metastability Analysis", William Evans, Eric Naviasky, Hao Tang...]
of which,
VL is the minimum valid logic level the comparator must generate in Volts, e.g: 0.8vdd = 0.96V for vdd=1.2V (doubts...??minimum CMOS voltage?)
AUL is the comparator's unlatched gain in V/V, for a strong arm latch without pre-amp, AUL=1
Q is the quantum size at the slicer input in Volts. For a 10bit ADC, Q=(vrefp-vrefn)/1024 = 0.8V/1024 = 780uV
T is the max time for slicer to make a decision in seconds. -> half tck used to trigger slicer.
4, Use pss (periodic steady state) analysis to simulate mestability of slicer. The Spectre RF shooting newton (pss) engine is the primary analysis used to characterize the dynamic comparator by obtain the periodic steady-state operating points (??). In addition from the periodic steady state, the circuit can be linearized and small signal analysis performed. The periodic steady state small-signal analysis is used for other comparator measurements, for example, noise. Shooting Newton analysis for the dynamic comparator uses the frequencies defined in the sources in the test bench. Transient noise can also be used for simulating comparator metastability.
Metastability is more like a parameter of bandwidth -> gain vs frequency. So, spec gives a metastability, calculation/simulation yields a curve of metastabiliby vs. design size(gain, speed) and parasitic cap.
How to simulate metastability -> T/Tm/AUL/Q -> how to estimate the Q in a data transceiver system?
[1] Cadence 2014 ADC Verification Workshop