一位前ARM工程師對RISC-V的批評

{"type":"doc","content":[{"type":"blockquote","content":[{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":"本文最初完成於幾年之前，彼時作者正在 ARM 公司擔任執行核心驗證工程師職位。"},{"type":"text","marks":[{"type":"strong"}],"text":"作者當時的工作深入或圍繞多種處理器核心，而文中提到的觀點深受這些經驗的影響，換句話說，這些觀點存在不同程度的偏見"},{"type":"text","text":"。"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":"作者依舊堅持認爲 RISC-V 的設計並不完美，但同時也承認，如果現在需要搭建一個 32 或 64 位的 CPU，他在實現構建時也會從現有工具中受益。"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":"本文主要基於 RISC-V ISA 規範 v2.0，部分已更新至 v2.2。"}]}]},{"type":"heading","attrs":{"align":null,"level":2},"content":[{"type":"text","text":"原文前言：一些觀點"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":"RISC-V ISA 對極簡主義的追求鑽了牛角尖，它極力強調減少指令數量，規範編碼等等。而這種追求則導致了錯誤的正交性（分支、調用、返回時重複使用同一指令），以及對贅餘指令的需求，這些在程序大小和指令數量上都會影響到代碼密度。"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":"以下面的 C 代碼爲例："}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"codeblock","attrs":{"lang":"null"},"content":[{"type":"text","text":"int readidx(int *p, size_t idx){ return p[idx]; }\n"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":"簡單的數組索引，非常常見的操作。將其在 x86_64 中編譯："}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"codeblock","attrs":{"lang":"null"},"content":[{"type":"text","text":"mov eax, [rdi+rsi*4]ret\n"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":"或者是 ARM 中："}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"codeblock","attrs":{"lang":"null"},"content":[{"type":"text","text":"ldr r0, [r0, r1, lsl #2]bx lr \/\/ return\n"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":"但是在 RISC-V 中需要的代碼則是："}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"codeblock","attrs":{"lang":"null"},"content":[{"type":"text","text":"# 很抱歉如果有任何語法錯誤，risc-v 並沒有在線編譯器slli a1, a1, 2add a0, a1, a1lw a0, a0, 0jalr r0, r1, 0 \/\/ return\n"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null},"content":[{"type":"text","text":"RISC-V 的極簡主義讓解碼器（CPU 前端）變得更簡單，代價則是需要執行更多的指令。然而，相對於拓寬流水線這個難題而言，解碼不規則指令的問題很好解決，主要難點在於確定指令的長度是否一致。x86 的衆多前綴就是個極佳的反面教材。對指令集的簡化不應追求極限。寄存器 + 移位寄存器的內存操作指令是程序中非常常見且簡單的操作，對於 CPU 而言也很容易實現。即使無法直接執行，CPU 也可以相對輕鬆地將其分步執行，其操作複雜程度遠遜色於融合簡單操作的序列。"}]},{"type":"paragraph","attrs":{"indent":0,"number":0,"align":null,"origin":null}}]}