關於異步復位同步釋放的原理不再贅述,直接貼 verilog 代碼如下:
1 module reset_sync (clk, rst_n, rst_n_sync); 2 input clk; 3 input rst_n; 4 output rst_n_sync; 5 //reg rst_n_sync; 6 7 parameter RST_WIDTH = 3; //一般兩級D觸發器即可極大降低亞穩態 8 reg [RST_WIDTH-1:0] rst_dff; 9 10 // asynchronous reset synchronous release 11 always @(posedge clk or negedge rst_n) 12 if (!rst_n) 13 rst_dff <= {RST_WIDTH{1'b0}}; 14 else 15 rst_dff <= {rst_dff[RST_WIDTH-2:0], 1'b1}; 16 17 assign rst_n_sync = rst_dff[RST_WIDTH-1]; 18 19 endmodule
綜合出的 3 級同步器 RTL 如下圖:
參考:https://blog.csdn.net/times_poem/article/details/51866520
https://www.cnblogs.com/yfwblog/p/4793118.html