1：設計一個二分頻器；
module count10(out,reset,clk);
output[3:0] out;
input reset,clk;
reg[3:0] out;
always @(posedge clk)
begin
if(out==9) out=-1;
if(reset) out<=0; //同步復位
else out<=out+1; //計數
end
endmodule
2：設計一個一位十進制計數器；
module half_clk(clk_in,clk_out);
input clk_in;
output clk_out;
reg clk_out;
always @(posedge clk_in)
begin
if(clk_in) clk_out=~clk_out;
end
endmodule
3：設計一個七段數碼管顯示譯碼器；
module decode4_7(data_out,indec);
output[6:0] data_out;
input[3:0] indec;
reg[6:0] data_out;
always @(indec)
begin
case(indec) //用case 語句進行譯碼
4'b0000: data_out = 7'b1000000; // 0
4'b0001: data_out = 7'b1111001; // 1
4'b0010: data_out = 7'b0100100; // 2
4'b0011: data_out = 7'b0110000; // 3
4'b0100: data_out = 7'b0011001; // 4
4'b0101: data_out = 7'b0010010; // 5
4'b0110: data_out = 7'b0000011; // 6
4'b0111: data_out = 7'b1111000; // 7
4'b1000: data_out = 7'b0000000; // 8
4'b1001: data_out = 7'b0011000; // 9
default: data_out=7'bx;
endcase
end
endmodule