module glitch(clk,data,q_out);
input clk,data;
output reg q_out;
reg q1;
always@(posedge clk)
begin
q1 <= data;
end
always@(posedge clk)
begin
q_out <= q1;
end
endmodule
module glitch(clk,data,q_out);
input clk,data;
output reg q_out;
reg q1;
always@(posedge clk)
begin
q1 <= data;
end
always@(posedge clk)
begin
q_out <= q1;
end
endmodule