序列檢測器Verilog設計

檢測10010的串

`timescale 1ns/10ps
module listcheck (rst,clk,in,result);
input rst,clk;
input in;
output result;
reg out;
assign result = out;
reg [2:0] current_state,next_state;
parameter [2:0]
  S0 = 3'b000,
  S1 = 3'b001,
  S2 = 3'b010,
  S3 = 3'b011,
  S4 = 3'b100,
  S5 = 3'b101;
//sequential state transition
always @ (posedge clk or negedge rst)
  if (!rst)
    current_state <= S0;
  else
    current_state <= next_state;
  //combinational condition judgment
always @ (current_state or in )
  begin
    next_state = 3'bx;
    out = 1'bx;
    case (current_state)
      S0: begin
           out = 1'b0;
           if(in) begin next_state = S1;end
           else begin next_state = S0; end
         end
      S1: begin
            out = 1'b0;
            if(!in) begin next_state = S2;end
            else if(in)begin
              next_state = S1;
            end
            else
              next_state = S1;
          end
      S2: begin
            out = 1'b0;
            if(!in)
            begin
              next_state = S3;
            end
            else if(in)
            begin
              next_state = S1;
            end
            else
            begin
              next_state = S2;
            end
          end
      S3: begin
            out = 1'b0;
            if(in) begin next_state = S4; end
            else if(!in)
            begin next_state = S0; end
            else begin next_state = S3;end
          end
     S4: begin
            out = 1'b0;
            if(!in) begin next_state = S5; out = 1'b1; end
            else if(in)
            begin next_state = S1; end
            else begin next_state = S4;end
          end
     S5: begin
            out = 1'b1;
            if(!in) begin next_state = S3; out = 1'b0; end
            else if(in)
            begin next_state = S1; end
            else begin next_state = S5;end
          end
     endcase
   end
endmodule

測試程序：

module listcheck_tb();
reg in,clk,rst;
wire result;
parameter sequence = 18'b1110_0100_1001_1100_10;
reg [4:0] i;
listcheck wt1(.in(in),.rst(rst),.clk(clk),.result(result));

initial
 begin
  in <= 0;
  rst <= 0;
 #5 rst <= 1;
  clk <= 0;
  end
  always #2 clk <= ~clk;

always@(posedge clk or negedge rst)
 begin
   if(~rst)
     begin
     i<=5'b0;
     end
   else if(i<=5'd17)
     begin
       in<=sequence[i];
       i<=i+5'd1;
     end
   else
     i<=5'b0;
 end
  endmodule

仿真波形：