Practise 1: Simple Wire
題目：
Create a module with one input and one output that behaves like a wire.
Unlike physical wires, wires (and other signals) in Verilog are directional. This means information flows in only one direction, from (usually one) source to the sinks (The source is also often called a driver that drives a value onto a wire). In a Verilog “continuous assignment” (assign left_side = right_side;), the value of the signal on the right side is driven onto the wire on the left side. The assignment is “continuous” because the assignment continues all the time even if the right side’s value changes. A continuous assignment is not a one-time event.
The ports on a module also have a direction (usually input or output). An input port is driven by something from outside the module, while an output port drives something outside. When viewed from inside the module, an input port is a driver or source, while an output port is a sink.
The diagram below illustrates how each part of the circuit corresponds to each bit of Verilog code. The module and port declarations create the black portions of the circuit. Your task is to create a wire (in green) by adding an assign statement to connect in to out. The parts outside the box are not your concern, but you should know that your circuit is tested by connecting signals from our test harness to the ports on your top_module.
翻譯：創建一個模塊，模塊包含行爲表現爲導線的一個輸入和一個輸出端口。
不像物理導線，在verilog內的導線是定向的。這就意味着信息是隻有一個流動方向的，從拉電流（通常只有一個）到灌電流（這裏拉電流通常稱爲驅動，意思是指將導線驅動爲某一個值）[ 作者注：這裏拉電流指的是端口向外電路流出電流，而灌電流指的是外電路流入端口的電流 ] 在verilog中，持續賦值（assign left_side = right_side）表示右端信號的值持續賦值給左端。賦值是持續的哪怕右端的值已經改變。一個持續賦值的事件不是一次性的。
模塊的端口也是有方向的（通常爲輸入和輸出端口）。一個輸入端口被外部其他的模塊驅動，輸出端口則驅動外部的某些端口。從模塊內部看，一個輸入端口就是一個驅動或者拉電流，而一個輸出端口就是一個灌電流。
下圖描述了verilog代碼生成電路的每一個部分的bit對應關係。模塊和端口聲明已經在黑色電路部分中創建好了。你的任務是創建一個wire（綠色表示）連接輸入端口和輸出端口，使用assign語句來描述。外面的電路部分你無需關心，但是你要知道你的電路是和外面的電路的測試線束相連接進行測試的。
解答
module top_module( input in, output out );
assign out = in;
endmodule
Practise 2: Four wires
題目
Create a module with 3 inputs and 4 outputs that behaves like wires that makes these connections:
a -> w
b -> x
b -> y
c -> z
The diagram below illustrates how each part of the circuit corresponds to each bit of Verilog code. From outside the module, there are three input ports and four output ports.
When you have multiple assign statements, the order in which they appear in the code does not matter. Unlike a programming language, assign statements (“continuous assignments”) describe connections between things, not the action of copying a value from one thing to another.
One potential source of confusion that should perhaps be clarified now: The green arrows here represent connections between wires, but are not wires in themselves. The module itself already has 7 wires declared (named a, b, c, w, x, y, and z). This is because input and output declarations actually declare a wire unless otherwise specified. Writing input wire a is the same as input a. Thus, the assign statements are not creating wires, they are creating the connections between the 7 wires that already exist.
翻譯
生成一個具有3個輸入端口和4個輸出端口的模塊，輸入和輸出端口的連接方式如下：
a -> w
b -> x
b -> y
c -> z
下圖描述了verilog代碼生成電路的每一個部分的bit對應關係。模塊和外部連接的部分有3個輸入端口和4個輸出端口。
當你有多個assign語句的時候，他們之間的出現順序並不重要[ 作者注：因爲這些assign語句都是並行執行的 ]。不像其他的編程語句，assign語句（持續賦值）只是描述事物之間的聯繫，並沒有將一個值從一個事物複製到另一個事物這一操作。
這裏需要將一種可能引起疑惑的地方進行澄清：這裏綠色的箭頭代表的是端口和端口之間的連接關係，並不是他們之間有導線相連接。模型本身已經聲明瞭7個線型的變量（命名爲a, b, c, w, x, y, 和 z）。這是因爲輸入和輸出端口在聲明的時候實際上就默認聲明爲線型變量除非有特殊的指定。聲明爲input wire a和聲明爲input a是一樣的。因此assign語句並沒有創造了一個線型變量，其聲明的7個線型變量之間的連接關係之前就已經存在。
解答
module top_module(
input a,b,c,
output w,x,y,z );
assign w = a;
assign x = b;
assign y = b;
assign z = c;
endmodule
Practise 3: Inverter
題目
Create a module that implements a NOT gate.
This circuit is similar to wire, but with a slight difference. When making the connection from the wire in to the wire out we’re going to implement an inverter (or “NOT-gate”) instead of a plain wire.
Use an assign statement. The assign statement will continuously drive the inverse of in onto wire out.
翻譯
創建一個應用了非門的模型
這個電路類似於wire那個題目，但是有輕微的不同。在創建輸入線型變量和輸出線型變量連接時，我們準備應用一個叫逆變器的器件（或者叫非門）而不是直白的一根線。
使用assign語句。assign語句將持續將輸入信號做非運算後的值驅動給輸出端口。
解答
module top_module( input in, output out );
assign out = ~in;
endmodule
Practise 4: 7458
題目
The 7458 is a chip with four AND gates and two OR gates. This problem is slightly more complex than 7420.
Create a module with the same functionality as the 7458 chip. It has 10 inputs and 2 outputs. You may choose to use an assign statement to drive each of the output wires, or you may choose to declare (four) wires for use as intermediate signals, where each internal wire is driven by the output of one of the AND gates. For extra practice, try it both ways.
翻譯
7458是擁有4個與門和2個或門的芯片。這次的任務要比7420芯片那次複雜一點點。
創造一個和7458芯片有同樣功能的模塊。已經存在10個輸入端口和2個輸出端口。你可能選擇用一個assign語句來驅動每個輸出端口，或者你可能會聲明4個線型變量用來間接連接各個內部線型變量經過與運算後的信號。作爲額外練習，兩種方式都試試吧。
解答
module top_module (
input p1a, p1b, p1c, p1d, p1e, p1f,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
assign p1y = (p1f & p1e & p1d) | (p1a & p1c & p1b);
assign p2y = (p2a & p2b) | (p2c & p2d);
endmodule