Vectors
題目
Vectors are used to group related signals using one name to make it more convenient to manipulate. For example, wire [7:0] w; declares an 8-bit vector named w that is functionally equivalent to having 8 separate wires.
Notice that the declaration of a vector places the dimensions before the name of the vector, which is unusual compared to C syntax. However, the part select has the dimensions after the vector name as you would expect.
wire [99:0] my_vector; // Declare a 100-element vector
assign out = my_vector[10]; // Part-select one bit out of the vector
Build a circuit that has one 3-bit input, then outputs the same vector, and also splits it into three separate 1-bit outputs. Connect output o0 to the input vector’s position 0, o1 to position 1, etc.
In a diagram, a tick mark with a number next to it indicates the width of the vector (or “bus”), rather than drawing a separate line for each bit in the vector.
翻譯
向量經常用於將相關信號用一個名字來進行分組，使其更加容易來進行控制。例如，
wire [7:0] w；
就描述了一個名爲w的8比特向量，其功能相當於擁有8個獨立的線。
需要注意的是，向量維度的聲明是放在向量名字之前的，相比於C的語法是不同的。但是在向量名字後面選擇向量的某些維度就如你所期 [ 作者注：下標的方向要和聲明時的下標方向保持一致，例如聲明時爲wire [7:0] w，那麼在調用的時候也應該調用爲w[7:0] ]。
wire [99:0] my_vector; // Declare a 100-element vector
assign out = my_vector[10]; // Part-select one bit out of the vector
創建一個擁有3比特的輸入和輸出向量的電路，同時也創建3個分離的1比特的輸出端口。將o0輸出端口和輸入端口0相連接，以此類推o1和o2。
在圖中，用線標記的並且有一個數字相挨着的線表示這個向量的寬度（或者叫“總線”），而分離的線則表示向量的每一個比特
解答
module top_module (
input wire [2:0] vec,
output wire [2:0] outv,
output wire o2,
output wire o1,
output wire o0 ); // Module body starts after module declaration
assign o0 = vec[0];
assign o1 = vec[1];
assign o2 = vec[2];
assign outv = vec;
endmodule
Vectors in more detail
題目
Vectors are used to group related signals using one name to make it more convenient to manipulate. For example, wire [7:0] w; declares an 8-bit vector named w that is equivalent to having 8 separate wires.
Declaring Vectors：
Vectors must be declared:
type [upper:lower] vector_name;
type specifies the datatype of the vector. This is usually wire or reg. If you are declaring a input or output port, the type can additionally include the port type (e.g., input or output) as well. Some examples:
wire [7:0] w; // 8-bit wire
reg [4:1] x; // 4-bit reg
output reg [0:0] y; // 1-bit reg that is also an output port (this is still a vector)
input wire [3:-2] z; // 6-bit wire input (negative ranges are allowed)
output [3:0] a; // 4-bit output wire. Type is 'wire' unless specified otherwise.
wire [0:7] b; // 8-bit wire where b[0] is the most-significant bit.
The endianness (or, informally, “direction”) of a vector is whether the the least significant bit has a lower index (little-endian, e.g., [3:0]) or a higher index (big-endian, e.g., [0:3]). In Verilog, once a vector is declared with a particular endianness, it must always be used the same way. e.g., writing vec[0:3] when vec is declared wire [3:0] vec; is illegal. Being consistent with endianness is good practice, as weird bugs occur if vectors of different endianness are assigned or used together.
Implicit nets：
Implicit nets are often a source of hard-to-detect bugs. In Verilog, net-type signals can be implicitly created by an assign statement or by attaching something undeclared to a module port. Implicit nets are always one-bit wires and causes bugs if you had intended to use a vector. Disabling creation of implicit nets can be done using the `default_nettype none directive.
wire [2:0] a, c; // Two vectors
assign a = 3'b101; // a = 101
assign b = a; // b = 1 implicitly-created wire
assign c = b; // c = 001 <-- bug
my_module i1 (d,e); // d and e are implicitly one-bit wide if not declared.
// This could be a bug if the port was intended to be a vector.
Adding `default_nettype none would make the third line of code an error, which makes the bug more visible.
Unpacked vs. Packed Arrays：
You may have noticed that in declarations, the vector indices are written before the vector name. This declares the “packed” dimensions of the array, where the bits are “packed” together into a blob (this is relevant in a simulator, but not in hardware). The unpacked dimensions are declared after the name. They are generally used to declare memory arrays. Since ECE253 didn’t cover memory arrays, we have not used packed arrays in this course. See http://www.asic-world.com/systemverilog/data_types10.html for more details.
reg [7:0] mem [255:0]; // 256 unpacked elements, each of which is a 8-bit packed vector of reg.
reg mem2 [28:0]; // 29 unpacked elements, each of which is a 1-bit reg.
翻譯
向量經常用來對相關聯的信號用一個名字來進行分組，使其更方便進行操控。例如：
wire [7:0] w;
聲明瞭一個名爲w的8比特大小的向量，等效於8個獨立的線。
向量的聲明：
向量必須被聲明爲如下形式：
type [upper:lower] vector_name;
type是向量的指定的數據類型，通常爲線網型或者寄存器型。type還可以再添加上端口的類型（例如輸入端口或者輸出端口）當你聲明一個輸入或者輸出端口時。舉一些例子如下：
wire [7:0] w; // 8-bit wire
reg [4:1] x; // 4-bit reg
output reg [0:0] y; // 1-bit reg that is also an output port (this is still a vector)
input wire [3:-2] z; // 6-bit wire input (negative ranges are allowed)
output [3:0] a; // 4-bit output wire. Type is 'wire' unless specified otherwise.
wire [0:7] b; // 8-bit wire where b[0] is the most-significant bit.
向量的末端性或者正式的說方向性是用來區分最低有效位是在較低索引處（小端）還是在較高索引處（大端）。[ 作者注：計算機裏的小端和大端的區別主要在於，小端表示是指數據高字節保存在內存的高地址中，而數據的低字節保存在內存的低地址中，大端表示是指數據的高字節保存在內存的低地址中，而數據的低字節保存在內存的高地址中，值得注意的是，大小端的保存順序的區別是以字節爲單位的而不是以比特爲單位的 ] 在verilog種，一旦一個向量用一種末端性聲明瞭，那麼就必須用同樣的方式來對這個向量進行使用。例如，用wire [3:0] vec; 來聲明的向量，使用的時候如果用成vec[0:3]就是非法的。保持一致的末端性是一種好的做法，奇怪的bugs發生往往就是在末端性上混亂使用導致的。
隱式網
隱式網通常是很難發現的bug。在verilog種，一個網型的信號，會由assign語句隱式的創建或者產生於一個沒有附加聲明的模塊端口上。隱式網總是一比特的線網型並且當你使用向量的時候會產生一些bug。如果想要禁止產生隱式網可以直接使用**`default_nettype none**
wire [2:0] a, c; // Two vectors
assign a = 3'b101; // a = 101
assign b = a; // b = 1 implicitly-created wire
assign c = b; // c = 001 <-- bug
my_module i1 (d,e); // d and e are implicitly one-bit wide if not declared.
// This could be a bug if the port was intended to be a vector.
添加**`default_nettype none**將會導致第三行代碼報錯，會使bug更顯而易見。 [ 作者注：該命令用於隱性線網指定默認線網類型。特別是在端口定義中，如果沒有顯示指定線網類型，那麼線網的類型爲wire（默認值）或者是由命令指定的線網類型 ]
未打包和打包：
你可能注意到在向量的聲明種，向量的索引長度是寫在向量的名字之前的。這聲明瞭數組的壓縮維度，特點是比特都是壓縮到一塊的（這裏和仿真相關，和真實硬件無關）。解壓縮數組的聲明是放在向量名字之後的。這種方式通常被用作聲明存儲數組。詳情見http://www.asic-world.com/systemverilog/data_types10.html for more details
解答
module top_module (
input [15:0] in,
output [7:0] out_hi,
output [7:0] out_lo
);
assign out_hi = in[15:8];
assign out_lo = in[7:0];
// Concatenation operator also works: assign {out_hi, out_lo} = in;
endmodule