目錄
2.2 read_timer_end_of_swap上下文切換
nxp rt Rt1050 測量結果，存儲介質 QSPI
1.測試結果展示
1.1 v1.13.0 驗證結果
BUILD: Mar 17 2019 10:29:20
starting test - Time Measurement
Timing Results: Clock Frequency: 600 MHz
Context switch : 124 cycles , 206 ns
Tick overhead :1747 cycles , 2911 ns
Thread Creation :2569 cycles , 4281 ns
Thread cancel :2276 cycles , 3793 ns
Thread abort :6361 cycles , 10601 ns
Thread Suspend :2137 cycles , 3561 ns
Thread Resume : 418 cycles , 696 ns
Thread Yield : 219 cycles , 365 ns
Thread Sleep : 308 cycles , 513 ns
Heap Malloc : 699 cycles , 1165 ns
Heap Free : 597 cycles , 995 ns
Semaphore Take with context switch : 394 cycles , 656 ns
Semaphore Give with context switch : 793 cycles , 1321 ns
Semaphore Take without context switch : 110 cycles , 183 ns
Semaphore Give without context switch : 906 cycles , 1510 ns
Mutex lock : 119 cycles , 198 ns
Mutex unlock : 162 cycles , 270 ns
Message Queue Put with context switch :1260 cycles , 2100 ns
Message Queue Put without context switch :1032 cycles , 1720 ns
Message Queue get with context switch : 931 cycles , 1551 ns
Message Queue get without context switch : 926 cycles , 1543 ns
MailBox synchronous put :7831 cycles , 13051 ns
MailBox synchronous get :1335 cycles , 2225 ns
MailBox asynchronous put :2163 cycles , 3605 ns
MailBox get without context switch :1017 cycles , 1695 ns
Timing Measurement finished
PASS - main
===================================================================
===================================================================
PROJECT EXECUTION SUCCESSFUL
1.2 v1.14.0 新版本測試結果
***** Booting Zephyr OS v1.14.0-rc3-27-g09e5acbe54dc *****
starting test - Time Measurement
Timing Results: Clock Frequency: 600 MHz
Context switch : 385 cycles , 641 ns
Interrupt latency : 0 cycles , 0 ns
Tick overhead : 0 cycles , 0 ns
Thread Creation :1686 cycles , 2810 ns
Thread cancel :3159 cycles , 5265 ns
Thread abort :6233 cycles , 10388 ns
Thread Suspend :5014 cycles , 8356 ns
Thread Resume :2481 cycles , 4135 ns
Thread Yield :1216 cycles , 2026 ns
Thread Sleep :1521 cycles , 2535 ns
Heap Malloc : 836 cycles , 1393 ns
Heap Free :1108 cycles , 1846 ns
Semaphore Take with context switch :9520 cycles , 15866 ns
Semaphore Give with context switch :1787 cycles , 2978 ns
Semaphore Take without context switch : 146 cycles , 243 ns
Semaphore Give without context switch :1674 cycles , 2790 ns
Mutex lock : 938 cycles , 1563 ns
Mutex unlock :2344 cycles , 3906 ns
Message Queue Put with context switch :2740 cycles , 4566 ns
Message Queue Put without context switch :1556 cycles , 2593 ns
Message Queue get with context switch :3039 cycles , 5065 ns
Message Queue get without context switch : 442 cycles , 736 ns
MailBox synchronous put :11013 cycles , 18355 ns
MailBox synchronous get :2699 cycles , 4498 ns
MailBox asynchronous put :5572 cycles , 9286 ns
MailBox get without context switch :3778 cycles , 6296 ns
Timing Measurement finished
PASS - main
===================================================================
===================================================================
PROJECT EXECUTION SUCCESSFUL
2.o sem1測試方法
void thread_sem1_test(void *p1, void *p2, void *p3)
{
k_sem_give(&sem_bench); /* sync the 2 threads*/
__read_swap_end_time_value = 1;
TIMING_INFO_PRE_READ();
sem_start_time = TIMING_INFO_OS_GET_TIME();
k_sem_take(&sem_bench, 10);
}
//main 函數 創建
sem1_tid = k_thread_create(&my_thread_0, my_stack_area_0,
STACK_SIZE, thread_sem1_test,
NULL, NULL, NULL,
2 /*priority*/, 0, 0);
k_sleep(1000);
/* u64_t test_time1 = _tsc_read(); */
sem_end_time = (__common_var_swap_end_time);
u32_t sem_cycles = sem_end_time - sem_start_time;
2.1 未有上下文測量
/* Semaphore without context switch*/
TIMING_INFO_PRE_READ();
u32_t sem_give_wo_cxt_start = TIMING_INFO_OS_GET_TIME();
k_sem_give(&sem_bench);
TIMING_INFO_PRE_READ();
u32_t sem_give_wo_cxt_end = TIMING_INFO_OS_GET_TIME();
u32_t sem_give_wo_cxt_cycles = sem_give_wo_cxt_end -
sem_give_wo_cxt_start;
TIMING_INFO_PRE_READ();
u32_t sem_take_wo_cxt_start = TIMING_INFO_OS_GET_TIME();
k_sem_take(&sem_bench, 10);
TIMING_INFO_PRE_READ();
u32_t sem_take_wo_cxt_end = TIMING_INFO_OS_GET_TIME();
u32_t sem_take_wo_cxt_cycles = sem_take_wo_cxt_end -
sem_take_wo_cxt_start;
2.2 read_timer_end_of_swap上下文切換
arch\arm\core\swap_helper.S
#ifdef CONFIG_EXECUTION_BENCHMARKING
stm sp!,{r0-r3} /* Save regs r0 to r4 on stack */
push {lr}
bl read_timer_end_of_swap
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
pop {r3}
mov lr,r3
#else
pop {lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
ldm sp!,{r0-r3} /* Load back regs ro to r4 */
#endif /* CONFIG_EXECUTION_BENCHMARKING */
/* exc return */
bx lr
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
SECTION_FUNC(TEXT, __svc)
/* Use EXC_RETURN state to find out if stack frame is on the
* MSP or PSP
*/
ldr r0, =0x4
mov r1, lr
tst r1, r0
beq _stack_frame_msp
mrs r0, PSP
bne _stack_frame_endif
_stack_frame_msp:
mrs r0, MSP
_stack_frame_endif: